A new class of insulating materials: Emergence of ultralow-k
09/01/2001
Jeffrey N. Bremmer Dow Corning Corp., Auburn, Michigan
overview
The continuous improvement of integrated circuit technology to smaller transistor device features with faster operating speeds has reached a critical juncture that calls for the development and integration of a new class of insulating materials. While the goal of these materials is to improve propagation delays, the ability to withstand IC processes such as CMP must not be overlooked.
As transistor scaling extends below the 0.18µm technology node, propagation delays associated with interconnects begin to bottleneck the operating speeds of transistors. New interconnect materials are needed to reduce the RC time constant associated with the delays. While integrating copper metallurgy in place of traditional aluminum has reduced the resistance component of the RC time delay, reducing the capacitance component will involve integration of a new insulating material with a lower dielectric constant (k) than the incumbent silicon dioxide dielectric material. Lower-k materials also reduce cross-talk between metal lines and minimize power dissipation.
The extent of dielectric constant reduction needed is dependent on transistor feature size. At the 0.13µm technology node, k<3 is targeted. While not production proven at the 0.13µm technology node, candidate low-k materials have undergone considerable integration development. Some IC makers have finalized their low-k material of choice. For example, IBM plans to finish integrating SiLK dielectric material into production by the end of this year; AMD, Motorola, and TSMC plan to produce devices with Black Diamond dielectric material [1]. Beyond the 0.13µm technology node, a dielectric constant of k<2.2 is targeted.
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With the exception of incorporating fluorine to reduce material polarity, achieving k<2.2 will involve reducing the density of dielectric materials. Pores consisting of air with k = 1 optimally lower dielectric constant, but integrating this new class of porous ultralow-k materials with k<2.2 performance presents a challenge. Since porous ultralow-k materials have unique material properties, some of the integration processes tailored for SiO2 will need redevelopment to yield reliable devices. Understanding the various options available for ultralow-k materials, their accompanying trade-offs in performance capabilities, and integration issues associated with the porous dielectric materials is critical for successful integration of an insulating material with k<2.2 dielectric constant performance.
Ultralow-k materials
Dielectric materials are categorized by the way they are deposited: low-k materials are either chemical vapor deposited (CVD) or spin-on applied. The incumbent dielectric material for ICs, SiO2, is deposited by CVD, a familiar technology to device makers. Thus considerable effort has been devoted to extend CVD dielectric materials to the k<2.2 performance regime. At this point, however, spin-on dielectric materials have been further developed for k<2.2, and are a growing segment of the dielectric materials market. Since their commercial inception in 1994, low-k spin-on dielectric materials have seen increasing use. FOx Flowable Oxide, a widely used spin-on low-k material, is employed in >20 production applications. Due in part to the ability to generate porous structures, further growth of spin-on dielectric materials is predicted for future generation ICs [2].
Several spin-on dielectric products have been introduced as candidate ultralow-k materials. The table highlights some of the materials, companies that are commercializing ultralow-k products, and typical properties of the dielectric material used as the host matrix for the porous materials. Three general types of matrix materials have been introduced as candidate ultralow-k materials in the porous form: silica, silsesquioxane, and aromatic organic. While the means of generating porosity and resultant pore size distribution vary, all these materials have been processed into porous films. Some offer the ability to tune the dielectric constant by controlling the volume fraction of porosity in the film. For example, XLK spin-on dielectric has demonstrated extendibility for several device generations with dielectric constant performance as low as k = 1.5 [3].
Challenges for ultralow-k materials
Performance requirements of ultralow-k materials for successful utilization in copper damascene integration are considerable. In addition to low-k requirements, the dielectric films should possess properties as close to the incumbent silica material as possible. These properties include low leakage current, low thermal coefficient of expansion, high dielectric breakdown voltage, low film stress, low moisture absorption, adhesion to other materials, high thermal conductivity, and mechanical strength. Realistically, porous ultra low-k material properties will not match those of silica. Properties are compromised when pores are incorporated into a dielectric material. For example, the porosity needed to lower the dielectric constant to k<2.2 causes a degradation of mechanical properties. Balancing low-k performance with sufficient mechanical properties to survive mechanically intensive integration processes such as chemical mechanical polishing (CMP) is one of the most significant challenges for ultralow-k materials.
To a great extent, it is the properties of the matrix material that determine the balance of mechanical and dielectric constant properties. Two-component composite models consisting of the matrix material and air can approximate properties of porous dielectric materials. For example, the dielectric constant is predicted quite readily with a two-phase parallel capacitance model, as shown in Eqn. 1. The model results in a simple linear relationship of k with pore concentration and is bound by the dielectric constant of the matrix for the nonporous material and by the dielectric constant of k = 1 for a fully porous structure consisting of air. Use of this model with the different ultralow-k material candidates indicates that the dielectric constant of the matrix material ultimately determines the concentration of pores needed to achieve a target effective dielectric constant. Specifically, porous silica requires more porosity than porous organic dielectric materials to achieve k<2.2 performance.
Mechanical properties are also approximated with a model as described in Eqn. 2. The degradation of modulus of elasticity (E) is approximated by a power function of film porosity. Since dielectric constant (k) can be predicted as a linear function of porosity, the balance of modulus of elasticity with dielectric constant (shown in Fig. 1) can be estimated as:
ke = kairp + kmatrix(1- p) (1)
Ee = Ematrix(1- p)mke = kairp + kmatrix(1- p) (2)
where ke = effective k; kair = k of air; kmatrix = k of matrix; Ee = effective E; Ematrix = E of matrix; p = pore volume fraction; and m = power coefficient to approximate E degradation.
For each type of porous dielectric material, Fig. 1 illustrates a degradation of modulus of elasticity relative to fully dense silica with E = 72 GPa. This degradation represents a challenge for chemical mechanical polish process engineers, wherein process development will clearly be needed to compensate for these softer materials. Of the three types of porous ultralow-k materials, porous silica appears to offer the most modulus of elasticity even though it requires greater pore concentration to achieve low k. Silsesquioxane materials demonstrate a range of mechanical property performance bounded between that of porous silica and porous organic dielectrics as shown in Fig. 1 for modulus of elasticity. Composition and resulting mechanical properties of silsesquioxane is process tunable by either synthesis or, for the case of hydrogen silsesquioxane (HSQ), by curing. As HSQ converts to a more silica-like film with lower Si:H bond density, modulus properties become more like that of silica. The influence of cure processing on modulus of elasticity for dense, nonporous HSQ films is shown in Fig. 2.
While modulus of elasticity has been shown to correlate with ability to survive CMP [4], it is not the only consideration for mechanical performance of dielectric materials. The ability to withstand stress without crack propagation, or fracture toughness, is also important. Like modulus, fracture toughness degrades with porosity. Modeling fracture toughness reveals that the softest of these materials, porous aromatic organic materials, show the most attractive fracture toughness capability [5].
Interestingly, not all mechanical properties are degraded by the porous structure of ultralow-k dielectric materials. One benefit of porous dielectric films is that once cured, there is less stress relative to their corresponding dense films. This allows for thicker films without propagation of cracks [6], a particular benefit for silsesquioxane type dielectric materials that can be susceptible to cracking.
Impact of pore structure on integration
During the integration of porous ultralow-k materials, there are further challenges, particularly maintaining low-k performance throughout damascene processing. Several integration process steps must be optimized to achieve intended capacitance reduction. Some process steps are impacted by the pore structure of the ultralow-k material.
Compatibility with wet chemical processing is influenced by pore structure. Open or connected pores are prone to absorb the wet chemicals used during various steps of integration such as via clean after photoresist strip. Water is a common rinse solvent with a k = 72 and any retained moisture in the pores of a dielectric material degrades the dielectric constant. Experiments with methylsilsesquioxane suggest that pore structure transitions from closed to open-cell at a pore concentration of ~20-30% [7]. As such, dielectric materials with low-k properties in the dense form are most amenable to closed cell porosity. However, while aromatic organic and methyl-silsesquioxane porous dielectric materials claim closed cell structures in combination with low dielectric constant performance of k<2.2, the significance of closed cell structure is not fully understood. If a chemical absorbs into a connected pore structure and does not chemically interact with the pore sidewall, it can also readily desorb with a short duration thermal treatment. Thus, development activities are under way to understand wet chemical compatibility and optimize the wet chemicals used during integration. One outcome of these activities is the determination that during copper damascene integration, acidic chemicals are compatible with porous HSQ dielectric materials for cleaning trenches after photoresist strip [8].
Another integration process impacted by the porous structure of ultralow-k dielectric materials is the barrier metal deposition process. The barrier metal in the trench and via sidewalls must be continuous to prevent Cu diffusion into the dielectric material and to facilitate electroplating of the Cu seed layer. Barrier metal layers become thinner with each new device generation; at the 0.10µm technology node, a <100Å thickness is targeted. Since barrier metal thickness is about the same dimension as ultralow-k materials' pore size, pore structure may impact the deposited layer's integrity. Although more research is needed to understand this topic, it is desirable to minimize pore size to reduce the effect on barrier continuity. Similar to pore concentration, pore size varies with the type of ultralow-k material and the method in which pores are generated. While difficult to compare pore dimensions because of the different methods available to characterize pore size, most porous silica and porous silsesquioxane materials report average pore sizes between 25 to 50Å. Some of the smallest pores, measuring 20Å, are generated from a material synthesized with a thermally decomposable organic porogen linked to an inorganic backbone. Larger pore sizes approaching 200Å are generated with porous aromatic organic materials.
Although there are new integration issues inherent with porous dielectric materials, they have not prohibited promising integration development. Several porous ultralow-k materials have been processed through copper dual damascene integration — JSR LKD [9], Dow Corning XLK [10], and Asahi ALCAP-S [11] — and have shown to maintain low-k properties through critical integration steps such as CMP, etch, ash, and clean. Key to dual damascene integration for these porous materials is the use of a trench first dual hard mask approach. Other porous ultralow-k materials such as Nanoglass E [12] and porous SiLK [13] have demonstrated feasibility in copper single damascene integration.
Continuous innovation and improvement
Due to the challenges associated with using porous dielectric materials, efforts are ongoing to improve ultralow-k materials. Some have undergone iterative developmental cycles to arrive at their current status. Nanoglass A, for example, was re-developed to the current Nanoglass E porous silica material to simplify the process of generating the porous structure, reduce pore size, and improve mechanical properties.
 Figure 3. Plasma curing improves mechanical properties when XLK spin-on dielectric converts to silica, as indicated by FTIR spectra. |
Other ultralow-k materials have also improved as a result of recent cure process innovations. Plasma cured XLK films generate improved mechanical properties relative to conventional furnace cured films [14]. The plasma process is applied using a mixture of H2, N2, and CF4 gases at treatment temperatures ranging from 200-230°C for 90 sec; the curing pressure varies from 2-4 torr. Unlike furnace cured films, plasma processed XLK films fully convert to silica without retained Si:H bonds, as is indicated in the Fourier transform infrared (FTIR) spectra in Fig. 3. Concomitant with conversion to silica is a significant improvement in modulus of elasticity — stiffness more than doubles. After rapid thermal processing (RTP), low dielectric constant performance is recovered. Further development of this technology is continuing, but the improvement in mechanical properties allows for greater potential success with mechanically intensive integration steps such as CMP.
Conclusion
As transistor scaling continues to 0.10µm and beyond, the need to reduce the RC time constant associated with interconnect delay requires the development and integration of ultralow-k dielectric materials. To achieve the targeted dielectric constant of k<2.2, pores will be introduced into the dielectric material. Each class of porous dielectric materials currently under development has a unique set of pore structure and property profiles that influences its ability to integrate.
Significant for all porous materials is the reduction of mechanical properties, which has led to efforts to accommodate these soft materials at mechanically intensive integration steps. In addition, further development is needed to understand the role of pore structure on compatibility with wet chemical processes and the ability to deposit a continuous barrier metal layer in the sidewall of trenches and vias. Although the challenges are considerable, initial integration results look promising. With combined continuous improvement of both ultralow-k dielectric materials and the integration processes used to fabricate metal interconnects, the fast operating speeds provided by transistors with <0.10µm feature sizes will soon become a reality.
Acknowledgments
FOx and XLK are trademarks of Dow Corning Corp. SiLK is a trademark of Dow Chemical. ALCAP is a trademark of Asahi Chemical. Nanoglass is a trademark of Honeywell. Black Diamond is a trademark of Applied Materials.
References
- Laura Peters, "Low-k Dielectrics Get Respectable," Semiconductor International, April 2001.
- "The Global Outlook for Dielectric Materials in Semiconductor Devices, 1999-2004," Kline and Company Inc., 2000.
- Hae-Jeong Lee, et al., "Correlations Between Structural Characteristics and Process Conditions of HSQ-based Porous Low-k Thin Films," Spring MRS Conference, April 2001.
- Simon Lin, et al., "Low-k Dielectrics Characterization for Damascene Integration," Proceedings of IITC, June 2001.
- Edward Shaffer, "Mechanical Integrity Drives Low-k Choices," Semiconductor Online, Nov. 2000.
- Craig Hawker, et al., "Supramolecular Approaches to Nanoscale Dielectric Foams for Adv. Microelec. Devices," MRS Bulletin, April 2000, pp. 54-58.
- Laura Peters, "Industry Divided on Low-k Dielectric Choices," Semiconductor International, May 2001.
- Francesca Iacopi, et al., "Studies on XLK Film Characterization and Integration in Copper Damascene Processes," Proceedings of Advanced Metallization Conf., Oct. 2000.
- K. Mosig, et al., "Single and Dual Damascene Integration of a Spin-on ultralow-k Materials," Proceedings of IITC, June 2001.
- R. Donaton, et al., "Physical and Electrical Characterization of Silsesquioxane Based Ultra-low-k Dielectric Films," Proceedings of IITC, June 2000; and Dow Corning news release, Dec. 2000.
- M. Hiroi, et al., "Dual Hard Mask Process for Low-k Porous Organosilica Dielectric in Copper Dual Damascene Interconnect Fabrication," Proceedings of IITC, June 2001.
- F. Zhang, et al., "Nanoglass E Copper Damascene Process for Etch, Clean, and CMP," Proceedings of IITC, June 2001.
- J. Waeterloos, et al., "Integration Feasibility of Porous SiLK Semiconductor Dielectric," Proceedings of IITC, June 2001.
- Q. Han, et al., "ultralow-k Porous Silicon Dioxide Films from a Plasma Process," Proceedings of IITC, June 2001.
Jeff Bremmer received his BS degrees in letters and engineering and material science engineering in 1987 from Calvin College and University of Michigan, respectively; and his MS in material science engineering in 1988 from U. Michigan, Ann Arbor. As an application development specialist for Dow Corning Corp., Bremmer develops and commercializes silsesquioxane materials for IC intermetal dielectric applications. Dow Corning Corp., 2200 W. Salzburg Rd., MS C041A1, Auburn, MI; ph 989/496-5448; e-mail [email protected].