Advanced processing: CMP of Cu/low-k and Cu/ultralow-k layers
09/01/2001
Shaumin Wang, Gautum Grover, Chris Baker, Jeff Chamberlain, Chris Yu Cabot Microelectronics Corp., Aurora, IL
overview
Extensive development in integrating Cu/low-k and Cu/ultralow-k technology with a CMP module is underway to ensure a seamless transition. This study focuses on the mechanical stability of these layers and develops one solution using traditional CMP technology.
Cu/low-k interconnect technology has become a critical technology for 0.1µm and sub-0.1µm IC device manufacturing due to the increased device speed, enhanced electromigration resistance, and improved scalability it affords. While the need for implementing a low-k dielectric has been demonstrated, a significant amount of work still remains in developing a viable, production-worthy interconnect technology that successfully incorporates such a low-k dielectric. Specifically, some porous ultralow-k candidates (k<2.2) exhibit relatively poor mechanical strength, low thermal conductivity, and possible compatibility problems with existing IC manufacturing processes.
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As shown in Table 1, a successful low-k candidate has to meet a wide range of performance criteria. In integrating Cu/low-k technology into a CMP module, one not only has to meet the stringent requirements of Cu CMP, such as good planarity, low defectivity, and corrosion prevention [1], but one must also ensure compatibility of low-k materials with CMP processing. Mechanical properties (such as Young's modulus and hardness) of a wide range of low-k and ultralow-k materials have been published [2-6], with most reporting a significantly lower Young's modulus and hardness for low-k and ultralow-k materials compared to SiO2. Clearly, weaker mechanical properties of low-k materials raise compatibility concerns with respect to CMP module integration, requiring further advances in low-k materials technology, optimization of consumable sets and polishing processes, and modifications of current process integration schemes to facilitate the adoption of Cu/low-k technology. One of the most critical challenges in developing a production-worthy CMP process is preventing delamination of the dielectric film. Although several alternate approaches to traditional CMP are being investigated [7], the data presented here suggest that Cu/ultralow-k structures can be successfully processed by strategic optimization of standard CMP technology.
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Sources of delamination include inferior adhesion, high internal film stress, and poor intrinsic mechanical strength. Prevention requires that slurries be able to polish wafers at mild CMP conditions but with desirable removal rates. The lower the k value, the milder the conditions (less mechanical action) required. This applies to both copper and barrier slurries. In addition, a hard mask is generally needed to cap the ultralow-k material. There are a number of different choices for such hard mask materials, each exhibiting different CMP behavior. One solution to addressing these diverse needs is with a tunable barrier slurry in which the polishing behavior of copper, barrier, and dielectric films, as well as hard masks can be tuned per the integration need.
Experiment
Both blanket and patterned 8-in. wafers were used in the experiment. The film stack consisted of a dielectric layer (SiO2, low-k or ultralow-k dielectrics), Ta barrier, PVD Cu seed layer, and electroplated Cu film. For patterned wafers, a capping layer was used on top of the low-k substrates. A number of low-k and ultralow-k materials were evaluated, including Dow Chemical's SiLK material (k ~2.7) and three ultralow-k materials with k values in the range of ~2.0-2.2. For patterned wafers, comb and serpentine test structures and Cu line array areas with linewidths ranging from sub-0.25µm to >10µm were used for electrical and planarity measurements, respectively.
Polishing was carried out on IPEC 472 and Applied Materials Mirra polishers, using Cabot Microelectronics' iCue 5003 copper and iCue 4200 barrier polishing slurries. Alternatively, a developmental second-step slurry from Cabot was used. Polishing rate selectivity information was collected for the Cu/SiLK wafers. Because of particular structure integrity issues for the ultralow-k materials, a polishing test using a down force and platen speed matrix, with down force from 1-5 psi, and platen speed from 20-100rpm, was performed. The goal was to evaluate the effects of polishing conditions on the compatibility of ultralow-k films with the CMP module, and to develop an optimized polishing process.
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Results and discussion
Table 2 summarizes the results on the Cu/SiLK wafers. A high selectivity of Cu to SiLK substrates was indicated and good mechanical and chemical compatibility was achieved through the use of a proper consumable set and process. The wafers were polished on an Applied Materials Mirra polisher. An IC-1000 pad stacked over Suba IV was used with the following tool parameters: membrane pressure in pounds; retaining ring pressure; inner tube pressure; and platen speed/carrier speed in rpm. These were 4, 4.5, 4, 63, 57, respectively, for Cu phase I; 2, 2.5, 2, 63, 57, respectively, for Cu phase II (soft landing); and 2, 4, 2, 103, 97, respectively, for barrier (Ta) polish. No delamination of the SiLK film was observed after polishing.
 Figure 2. SEM image of a Cu/low-k wafer showing delamination in low-k film. |
As expected, we observed that the likelihood of delamination increases with decreasing material mechanical strength. For a standard CMP process, delamination occurs when the film's mechanical strength drops below a threshold level (Fig. 1). This threshold depends on a number of factors, including polishing parameters such as down force and platen speed. Figure 2 shows an example of film failure due to delamination. In general, we observed pattern-dependent delamination with vulnerable spots located in a die's large, open areas.
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Figure 3. a) Optical micrographs of delamination sites in two die on the same wafer. Note that the delamination occurred in the same open field area in each die. In each case, it is adjacent to the upper left corner of the dense array (see arrow). b) Optical micrographs of nondelaminated films, at the same site shown in Fig. 3a, shown at higher magnification. Note the presence of an apparent deposition defect at the corner of the dense array adjacent to the open field area.
Results from a number of recent studies are summarized in Table 3 in order to understand the possible correlation between the mechanical properties (and therefore propensity to delamination) and dielectric constant. Materials with lower dielectric constants also tend to have a lower mechanical strength, possibly due to increased porosity and pore sizes.
With the goal of eliminating film delamination during CMP of ultralow-k films, an optimized polishing process was developed that uses a set of more moderate polishing conditions while minimizing the impact of these modifications on throughput. In this experiment, down force, platen speed, and carrier speed were varied. The film stack, slurry chemistry, slurry flow rate, pad type, and pad conditioning were held constant. Delamination was determined qualitatively as either "yes" or "no" by visual inspection using optical microscopy.
While results from one ultralow-k material will be discussed here, comparable results were obtained for the other two materials. The results showed that, with a down force <3psi and platen speed <40rpm, delamination of the film stack could be prevented. Delamination occurred more readily with this particular ultralow-k material as the down force or platen speed was increased above these moderate conditions. Inspection also indicated that certain areas on the wafer were more prone to delamination than others. Figure 3a shows gross delamination occurring most often in open field areas adjacent to dense arrays. The "spots" were typically >1mm2 and appeared in more than a dozen places at regular intervals across the wafer. When compared to the film surface prior to polishing, the delaminated site usually contained a film deposition defect (Figure 3b). These observations indicate that delamination correlates to specific patterned features and/or deposition defects.
 Figure 5. Probability distribution (%) of contact resistance, with data collected using a two-step CMP process. |
In terms of electrical performance, serpentine line resistance and contact resistance on a number of Cu/low-k test structures are shown in Figs. 4 and 5, respectively. Each device structure underwent a two-step CMP process. Figure 4 shows a relatively tight line resistance distribution, while Fig. 5 indicates a reasonably low contact resistance (~1W/contact at 70%). Note that the minimum line width is 0.25µm and the two graphs per data set represent experimental results obtained on two different commercially available CMP polish tools. A perfect data set would be a straight vertical line with 100% probability. The preliminary data look encouraging.
Conclusion
We have evaluated integration of Cu/low-k and Cu/ultralow-k interconnect technology with a CMP module. For the low-k material tested (Dow Chemical SiLK), good compatibility with CMP has been achieved. While for ultralow-k materials, delamination has been observed, delamination appears to be pattern-dependent and initiated from specific pattern features on a die, particularly in the presence of what appears to be deposition defects. We have demonstrated that, using an optimized polishing consumable set and a moderate polishing process, delamination could be significantly reduced or eliminated. Based on these preliminary results, CMP is suited for IC device generations using Cu/ultralow-k interconnect technologies.
Acknowledgment
Paul Lefevre, International Sematech, is an additional author of this paper. The authors wish to thank Dow Chemical for providing Cu/SiLK wafers and to acknowledge contributions to Cu CMP technology development from Vlasta Brusic, Joe Hawkins, Isaac Cherian, David Schroeder, Lisa Lindzy, Colin Schmidt, David Garcia, and Kyle Miller. iCue is a trademark of Cabot Microelectronics.
References
- V. Brusic, "Cu Corrosion Mechanisms and Control," invited paper presented at AMC Conference, San Diego, Oct. 3-7, 2000.
- H. Hanahata et al., Proc. 2000 IITC Conf., p. 61, 2000.
- R.D. Miller et al., Proc. Advanced Metallization Conference 1999, p. 327, 2000.
- C. Jim et al., Proc. 2000 IITC Conf., p. 99, 2000.
- T. Furusawa et al., Proc. 2000 IITC Conf., p. 222, 2000.
- M. Engelhardt et al., Proc. Advanced Metallization Conf. 1999, p. 417, 2000.
- F. Kaufman, "Enabling Planarization for the Twenty-First Century: Opportunities, Challenges, and Alternatives," invited paper presented at the CMP Symposium, Semicon West, San Francisco, 2000.
For more information, contact Shumin Wang at Cabot Microelectronics Corp., 500 Commons Dr., Aurora, IL 60504; ph 630/375-5553, fax 630/585-9976.