Techniques to improve Cu/low-k integration

09/01/2001

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COVER FEATURE

Victoria Shannon, Novellus Systems, San Jose, California

overview
The challenge for the semiconductor industry is to bring new technologies into high-volume manufacturing in the shortest possible time at minimum cost. This article describes some results of equipment supplier alliances intended to minimize the time from development to high-volume manufacturing for integrating copper/dielectric processes.

A next-generation PECVD system designed to deposit low-k dielectric films, Novellus' SEQUEL Express employs a multistation sequential deposition architecture and has a maximum throughput >110 wph. Photo courtesy of Novellus Sytems Inc. Click here to enlarge image

The explosion in Internet usage and wireless communications has driven an unparalleled demand for cost-competitive, high-performance computing, communications, and information technology products. The challenge for the semiconductor industry in meeting this hunger for new and more sophisticated products is to bring new technologies into high-volume manufacturing in the shortest time and with the minimum development and manufacturing costs. As a result, over the past few years, the industry has seen the formation of a number of alliances and a proliferation of licensing agreements among device manufacturers to share the burden of development. This article discusses problems related to the integration of low-k materials and copper, and root-cause solutions that have been developed through a collaborative effort called the Damascus Alliance.

Cu/dielectric barrier adhesion
Adhesion loss in a copper dual damascene structure can occur for a variety of reasons at different interfaces. Copper forms a native oxide that can interfere with adhesion. If not completely removed from the copper surface during the copper oxide reduction step prior to dielectric deposition, the copper/dielectric diffusion barrier interface will be weak. In addition to adhesion problems, our data indicate that the presence of residual oxide could limit the time-dependent dielectric breakdown performance, as seen elsewhere [1].

Figure 1. Processes performed at the Customer Integration Center, a 20,000 ft2 Class 1/Class 100 cleanroom, include via/line dielectric and antireflective deposition; via and line etch; and photoresist and residue removal. Metallization is performed by Cu electrofill, followed by CMP.Click here to enlarge image

Dielectric diffusion barrier adhesion to the copper interface can be compromised even when a small amount of residue is left on the copper surface following CMP. Removing the organics at the interface by either a pre-treatment step — such as an aggressive hydrogen containing plasma — prior to dielectric deposition or by removing the corrosion inhibitor from the CMP process (generally BTA) can address this issue. Residues left from the wet clean following the barrier open step can also be a problem in the exposed via areas. An example of an affected area is shown in Fig. 2, where blistering can be observed in a bondpad structure with underlying vias. Again, this can be addressed by optimizing the wet clean or by a pre-treatment prior to dielectric deposition.

Finally, to successfully integrate copper with a fluorine-containing SiO₂-based low-k material (fluoro-silicate glass, FSG), there are special considerations. In particular, the F bonds in many FSG films are reactive, especially with water [2], and can react during other process steps to produce free fluorine. At the metal diffusion barrier interface, Ta reacts with the free fluorine to form volatile by-products at elevated temperatures. The weakened interface can fail when subjected to the stress of an overlayer, such as the dielectric diffusion barrier. A number of solutions exist; among them a re-use of: a TaN or bilayer TaN/Ta diffusion barrier, a more stable FSG film, and a hydrogen treatment to remove the mobile fluorine from the exposed surface prior to deposition.

Defect reduction: Cu hillocks
Copper hillocks can be a significant problem [3], with effects ranging from saturating defect metrology, such that other significant defects cannot be monitored, to causing electrical shorts between metal lines. Hillock formation is influenced by multiple factors such as stress, thermal history, surface condition, grain size, and orientation. Most significant is the thermal history of the copper film.

Figure 2. Plan view and FIB cross-sections of a dielectric diffusion barrier-copper interface indicate the loss of adhesion.Click here to enlarge image

Most dielectric barrier depositions are performed at process temperatures near 400°C. The wafer is inserted into the chamber and is placed on a heated surface where it thermally equilibrates. The process gases start flowing and the flow setpoints are stabilized. A plasma is then lighted and stabilized, and a pre-treatment reduces the native oxide and enhances adhesion. The gas flow setpoints are changed; again the plasma is lighted and stabilized, and the diffusion barrier is deposited. This takes some time, with the bare copper surface exposed at a temperature high enough to start grain growth on the copper surface. The kinetics of the surface cause hillocks to form as the thermally induced stress relaxes.

Figure 3. The number of copper hillock defects b) is dependent on exposure to high temperatures prior to dielectric diffusion barrier deposition a). (Used by permission of Novellus equipment user) Click here to enlarge image

The key to managing copper hillock formation is much the same as for aluminum [4]: minimize the time at elevated temperatures prior to the deposition. Films that have already been thermally cycled to recrystallize the copper and enhance the electromigration performance are not as prone to hillock formation, since the film has larger grains and fewer grain boundaries. Particularly effective are long-duration, low-temperature furnace anneals.

Figure 4. Photoresist poisoning is indicated in via arrays after trench patterning in a) cross-section and in b) plan view. Poisoning was prevented c) when the dielectric film was not exposed to a nitrogen-containing plasma. Click here to enlarge image

Figure 3a shows a SEM cross-section of a copper hillock defect. Note that the hillock is a single grain growing out of the plane of the surface. The conformal deposition of the dielectric diffusion barrier indicates that the defect occurred prior to the deposition. Figure 3b shows that the number of copper hillock defects depends on the length of time that the bare wafer is subjected to high temperatures prior to dielectric diffusion barrier deposition.

DUV photoresist poisoning
Photoresist poisoning is a particular problem when deep-ultraviolet (DUV) photoresists are used in conjunction with copper and low density or nanoporous low-k materials, materials targeted for the 0.13µm generation and below. DUV photoresists use a chemical amplification process, which is dependent on photogenerated acids produced during the exposure step. Neutralization — or poisoning — of the photogenerated acids can result in the inability to develop the exposed resist [5].

Figure 5. Via voids (lower right), a function of post electrochemical deposition thermal treatment (left), are measured by voltage contrast SEM (upper right). (Used by permission of Novellus equipment user)Click here to enlarge image

When low-density or nanoporous materials are exposed to nitrogen containing plasmas, the resulting amines trapped in the film can diffuse out and effectively poison the photoresist (Fig. 4). Amines can be diffused readily in most low-density and nanoporous materials, with diffusion lengths greater than hundreds of microns. The deposition processes, as well as etch and strip, must therefore be designed to avoid exposing the low-k film to any source of nitrogen. If a capped low-k film is used, resist poisoning may not be observed at the via lithography step, but poisoning will occur at the trench lithography step as a result of the exposed sidewalls of the vias following the etch [6].

Via yield degradation
Via yield degradation with thermal cycling has a clear impact on device yield [7], becoming more significant as geometries are reduced. The dominant factor in via stability is the thermal treatment of the device following copper electrodeposition with the overburden (excess material that is subsequently polished away) in place. The copper film expands more than the oxide trench enclosure, which induces a compressive stress in the copper layer. Grain growth occurs and the stress relaxes through dislocation motion. During the cooling phase the copper contracts and goes into tensile stress, inducing voids (via "pull out" — Fig. 5). To best manage void defect formation, thermal treatment with the copper overburden in place should be limited to temperatures where the copper can expand and contract reversibly, without going into plastic flow [8].

Figure 6. The reliability of a 50Å TiN(Si) metal diffusion barrier relative to the industry standard 300Å Ta diffusion barrier under bias-temperature-stress conditions (250°C, 3MV/cm). New processes and materials for advanced device generations can be tested under rigorous conditions prior to beta testing in actual device structures.Click here to enlarge image

Other factors can influence via yield degradation, particularly adhesion at the copper-metal diffusion barrier and the copper-copper interfaces in the bottom of the via. Good adhesion at these interfaces can resist the tensile force, thereby reducing void formation. Thus, any process step that modifies these interfaces can also modify via yield after thermal cycling. Examples are: the PVD pre-clean step prior to barrier/seed deposition; the wet clean process following the dielectric barrier open step in the via; the metal diffusion barrier material and deposition conditions; and the seed deposition conditions. Additionally, our studies have indicated that incomplete fill can also play a role due to void migration as the stress relaxes.

Accelerating time to market
Basic integration studies on future materials and processes developed in R&D can accelerate the time to implementation for new materials and simplify the integration task for device makers. Such integration studies can effectively screen new materials so only processes that show improvement in the baseline process are released.

An example of such a study is shown in Fig. 6. A new conductive copper diffusion barrier film, CVD TiN(Si), developed by Novellus for future technology requirements, has been tested in device structures prior to beta testing at a customer site. The reliability of TiN(Si) under bias-temperature-stress conditions (250°C, 3MV/cm) shows that 50Å of the new copper diffusion barrier has superior performance to 300Å of Ta, the industry standard copper diffusion barrier. With a nominal sidewall thickness of 3nm, this diffusion barrier technology will easily extend to the 70nm node.

Conclusion
It is clear that the issues related to the integration and thermal treatment of copper-containing devices are very complex and are not completely understood. The integration of low-k materials into copper containing devices provides yet another level of complexity that must be dissected and understood. Because of this, the equipment industry is stepping up to the challenge of not only providing unit processes but integration support as well.

References

1. J. Noguchi, et al., Proc. IRPS 2000, pp. 339-343.
2. H. Yang, G. Lucovsky, J. Vac. Sci. Tech, pp. 1515-1518, May/June 1998.
3. C.C. Lin, et al., Proc. IITC 2001, pp. 113-116.
4. E.P. Van de Ven, et al., Proc. VMIC 1987, pp. 434-438.
5. C.P. Soo, et al., IEEE Trans. on Semic. Manuf., pp. 462-469, Nov. 1999.
6. T. Mountsier, et al., to be published.
7. T. Oshima, et al., Proc. IEDM 2000, pp. 123-126.
8. G.B. Alers, et al., Proc. IRPS 2001, pp. 350-354.

Acknowledgments
The author would like to acknowledge the work of the following individuals from Novellus Systems, upon which much of this discussion was based: Bart van Schravendijk, Mahesh Sanganeria, Glenn Alers, Tom Mountsier, and Gary Ray, and the staff of the Customer Integration Center (Fig. 1), where this work was performed. I would also like to thank the many customers we have worked with to address these issues and especially those who have been so kind as to provide some of the figures included in this work.

Victoria Shannon received her PhD in physical chemistry from the University of California at Berkeley. She is VP of technology, integration, and applications at Novellus Systems, coordinating the technology efforts of Novellus' business units. Novellus Systems Inc., 4000 N. First St., San Jose, CA 95134; ph 408/922-4814; e-mail [email protected].