Technology News
08/01/2001
New technology tackles maskmaking challenges
Lithographers focused on new ways to deal with the increasing complexity of maskmaking at an intense Advanced Reticle Seminar in Santa Clara recently. This seminar was the seventh sponsored by Ultratech, but Numerical Technologies will take over as chief sponsor next year.
One highlight was a description of a new architecture for a laser pattern generator to make reticles at 130nm and beyond presented by Jorge Freyer, president of Micronic Laser Systems, Sweden and Mountain View, CA. Unlike a raster-scan e-beam mask writer, the new Sigma 7100 works more like a stepper. It uses a silicon light modulator (SLM) with a micromirror array and an aperture plate to illuminate billions of pixels in parallel with a single laser flash.
 Micronic Laser Systems' Sigma 7100 laser pattern generator has a new architecture to make reticles at 130nm and beyond. |
The SLM writer (based on MEMS work at Fraunhofer Institute) makes use of reduction optics to reflect the laser light. A CMOS chip under the micromirror array provides signals to deflect the highly reflective aluminum-coated mirrors (each 16x16µm square), about 60µm from full on to full off, with gray scale capability. The pattern of micromirrors reflecting laser light through the aperture plate forms the mask features with 100nm pixels at full on. Partially deflecting the mirrors allows dose modulation for a smaller address grid — since light from the laser flash is scattered and less gets through the aperture plate — to place the sharp edges of features, and also for diagonal features.
Each image is repeated in four passes, each offset a little more than one pixel. For 130nm devices, using a 248nm laser at a 1 kHz flash rate, a NA of 0.72, and a million micromirrors, a reticle for a 100x100mm chip takes about three hours, according to Freyer. For 70nm features, a 193nm laser at 2 kHz flash rate and NA of 0.82 would be used. A preprocessor CPU "farm" of 50 microprocessors, rasterized in FPGAs, prints in block fashion at about 3 billion pixels/minute.
Beta sites, including DuPont Photomasks, have been using the Sigma 7100 laser pattern generator for several months now, according to Micronics.
In another interesting part of the seminar, David Trost of ETEC, a subsidiary of Applied Materials, described aeroglide technology for a new generation of MEBES e-beam maskmaking machines. This technology puts air bearings in a vacuum stage and reduces vibration in the new MEBES-X from 25-50 mg for the traditional platform down to <1mg, said Trost. In the new platform, there are no vibration sources, rolling elements, friction drives or inertial walkers, etc.
In comparison to the previous technology, air bearings were outside rather than inside the vacuum; ball screws replaced linear motors; and compliant — not rigid — structures were used. Motion is controlled not only in x and y, but also in the theta (angular) axis.
Getting the air bearing (which uses dry nitrogen to curb contamination) into a vacuum was no mean feat. In the differentially pumped air bearing, gas at 120psi is forced down the center of a journal, with a series of annuli below feeding the gas into pumps. The stage sits on three points using no clamps, and the center of the mask is always fixed. A model even allows prediction of a few nanometers of displacement due to temperature effects on the mask, so compensation is feasible. The Aeroglide has three orders of magnitude less vibration than the current best Mebes platforms, down to 50µg, according to Trost.
One of the most interesting asides during a lively panel session came from Harry Levinson, manager of AMD's litho tools department. He said that Chris Spence of AMD had been studying the effects of optical proximity correction (OPC) on wafers, and often found no discernable difference, so in these cases it was a waste of money and time. Levinson also added a corollary to "the customer is always right" motto. The customer may pick the technology, Levinson said, "but he might not like the price!" He suggested that while $15,000 might buy an attenuated phase shift mask (PSM) on an Alta system, an alternating aperture PSM might cost $40,000.
Packson Chen, a founder of Taiwan Mask Corp., suggested that a critical layer mask might cost $60,000. He indicated that a model must be developed for OPC corrections. Levinson also complained that chipmakers want masks too fast, not realizing that the data involved has risen several orders of magnitude. Mircea Dusa, senior imaging scientist for ASML, said it might take 40 days for a full set of masks.
Inspection problems must be addressed, AMD's Levinson indicated. For example, different wavelengths are used for exposure and inspection, so you can't actually see what you print. You may identify a problem, he said, but not know how to fix it on a PSM. Linewidth control demands for leading edge circuits are beyond current capabilities due to mask error factor, Levinson added. ASML's Dusa also pointed out that different tools may not produce uniform critical dimensions (CDs), so that reticles must be matched to tools. He suggested doing cross correlations between reticles and printing. Dusa said the tools might not yet be available to deal with problems like nonlinear problems with dense circuitry. Near-neighbor effects may show up in electrical tests, but thousands of measurements may be needed to determine causes.
Takeaki Ebihara of Canon described one approach to cutting costs for PSMs in a presentation co-authored by Marc D. Levenson, consultant and editor of Microlithography World. Ebihara cited many issues with conventional strong PSMs, including imaging anomalies, the impossibility of inspection and repair, damage during cleaning, difficult design, high cost, and low throughput. The sidewall-chrome alternating aperture mask (SCAAM) approach that Canon is investigating addresses these concerns. The Phase Phirst method developed by Levenson for lower cost strong PSMs was detailed in Solid State Technology, Jan. 2001, p. 104.
Work with bi-layer materials and a two-step quartz etching process for phase shift masks was described by Yasutaka Morikawa of Dai Nippon Photomasks (DNP). He said that DNP had been delivering defect-free alternating PSMs for the past 13 months. But new shifter materials will be needed for argon fluoride lithography, he said. He described a structure using TaSiO3 for the shifter, and TaCr for the transmittance control layer on top of quartz.
An update on 157nm reticle development work revealed many remaining challenges. Roxanne Engelstad, U. of Wisconsin, said so far there is no decision about whether to use thin (polymer) or hard pellicles, an important choice in developing static models to find image placement error. The error budget must be pushed below 10nm, she said. There is a problem with temperature coefficients between aluminum frames and the glass reticle and also with adhesive qualities.
The search is still on for monomers that can withstand radiation but have good transmission at 157nm, according to Joe Gordon, DuPont Photomasks' Pellicle Division. Thick pellicles (300- 80µm) of modified fused silica cause distortion, while a thin polymer membrane, about a micron thick, would have low optical distortion. So far some 200 materials — extremely low absorption compounds but not yet polymers — have been investigated. This work has led to materials with 97% transmittance, but darkening, possibly related to some traces of metals and inorganic solvents, is still a problem
Terapixel inspection rates are possible with the Terastar reticle inspection system described by William Volk of KLA-Tencor, jointly developed with TSMC. The existing Starlight system was redesigned using three laser beams (top, mid, and bottom levels), a holographic beam splitter, and a new XPA die-to-die algorithm. The new instrument can perform concurrent die-to-die and contamination inspections using a new Tera image computer working at 150 megapixels/sec in transmitted or reflected mode. Because of the shift from 488nm blue to 364nm ultraviolet light, the die-to-die algorithm had to be redesigned, according to Volk.
This system avoids hang-ups on massive defects and also saves defect images for inspection. A new algorithm is being developed for alternating PSMs, Volk said, that will be easier to use because of fewer false defects. KLA-Tencor is also working on pushing defect sensitivity below 100nm and developing a die-to-database algorithm.
Faster, cleaner wafer cleaning is achieved by using a 172nm eximer laser, according to Bill Melzger of Ushio, which provides the lamps and housing to makers of wafer cleaning tools. One toolmaker is also investigating the laser cleaning process for resist removal.
Patented IC measures time to trillionths of a second
Ken Condreva, an engineer at Sandia National Laboratories, Livermore, CA, has built a better electronic stopwatch. It's an IC, dubbed Falcon, accurate to 125 psec. While Condreva's inspiration for his invention was the need to accurately record critical timing signals in weapons test flights, where new telemetry systems require compact, lightweight, and low-power devices, Sandia officials expect additional commercial applications.
This timing device accurately operates in normal working conditions and in extremely rugged and harsh environments, including high and low temperatures, high vibration and shock, and high and low humidity. Small and inexpensive battery-operated monitors could also be devised for future innovative uses.
The Falcon IC is fabricated with standard CMOS technology and could be inexpensively manufactured by most semiconductor manufacturers. Sandia is currently seeking commercialization partners with the imagination to exploit this robust and innovative technology.
Prior to this invention, "the only thing that had this resolution were table-top instruments packaged in a box. They were way too big, and used way too much power," says Condreva. Falcon uses a patented "pulse stretcher" technique to increase resolution up to 200 times for a low-power electronic clock using 300mW at 40Mhz; it is a compact way to count a time interval at high resolution with low power. The circuitry provides greater resolution by lengthening the duration of the output signal, making it last from 64-200 times longer than the input signal. In effect, the input pulse is "stretched" in real time, similar to recording a sporting event with fast-action film and replaying it at slow speed to clearly see what happened.
Briefly explained, the FALCON accepts standard CMOS level input signals (i.e., START and STOP inputs). Both inputs are fed to "pulse stretcher" circuits that measure the elapsed time between the input signal transition and the next clock signal transition. A main counter also keeps track of the number of clock periods between the START and STOP inputs. These three measurements are combined in a processor to obtain the time interval result.
An alternative to solid polyurethane for CMP
A new chemical mechanical polishing (CMP) pad by Thomas West Inc. has shown a reduction in slurry consumption up to 40%, high removal rates using industry standard slurries, and extended pad life, according to Karey Holland, TWI's VP of technology. CMP, a critical process step in device manufacturing, is one of the fastest growing semiconductor equipment markets. The consumables, pads, and slurries for copper CMP can comprise up to 60% of overall COO.
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For optimum polishing, different pads are used for metals and oxides because of different requirements — porousness for metals, hardness for oxides — to ensure uniform distribution of the slurry. Traditionally, hard pads have been effective for planarization and minimization of dishing problems, but have had considerable challenges in attaining and maintaining slurry at the wafer/pad interface and maintaining low defect levels. A soft pad can present a challenge in achieving acceptable planarization. TWI's Right Pad 711 (see figure) has been designed to best utilize favorable characteristics of both pad types.
Standard solid polyure-thane pads, typically used for tungsten and copper polishing, are formed in 3 ft high, 3 ft dia. molds. Baked overnight, cross linking of the outer surfaces differs from that of the center, creating differences in Shore D hardness — low 60s on the surfaces and low 50s within. The result is a 15-20% variation in removal rates. Surface roughness and k-grooves transport the slurry.
TWI's 711, consisting of polyester fiber impregnated with polyurethane, combines the hardness of solid polyurethane with the porosity of nonwoven polyester, suitable for polishing both metals and oxides. Holland said pad uniformity is built into the process in which polyester and polyurethane are combined, formed in a continuous flow, and cut into sheets. The resulting material is harder than polyurethane (better than 50) and stiffer than polyester. In at least one case study comparing the 711 with solid polyurethane, 711 had a 20% higher removal rate with metal slurries, improved chemical distribution, and lower wafer-to-wafer nonuniformity. Slurry consumption was reduced to <100 ml/min.
"With our process, each pad is virtually identical, allowing our customers to achieve reduced set up times, overcome the challenge of recalibration due to pad-to-pad variability, and improve variation in removal rates to 3-5%," noted Holland.
Compared to a standard solid polyurethane pad (l), the polyurethane-embedded nonwoven polyester pad (r) has an open-cell structure that reduces slurry consumption and has a hardness >50.
STATS steps up role of package modeling
Addressing the demanding short time to market for complex IC package designs, ST Assembly Test Services Ltd. (STATS), Singapore, has seen US success and is expanding simplified package modeling (SPM) services to customers in Europe and Asia, said Roger Emigh, manager of package characterization.
SPM is particularly advantageous for thermal simulation of the industry's growing number of complex package configurations, including nonsymmetrical, stacked die (see figure), and other multichip packages, according to Emigh. Traditional thermal simulation methods analyze semiconductor devices based on final package design drawings and finite element analysis calculations. With SPM, however, rather than waiting for the completion of the final substrate or leadframe, design modeling is done as soon as a customer identifies the basic package design requirements — the package type, die size, number of solder balls, copper layers, etc.
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SPM relies on creating a simplified model that matches an experimentally tested design and is similar, but not identical, to the customer design. The simplifications involve combining discrete elements within the package, such as traces, bond wires, or lead frame fingers, into larger blocks of material. These "cuboids" are assigned an effective thermal conductivity that produces the correct thermal behavior during the simulation process. Other materials within the package that are thin, such as the die attach adhesive layer, are collapsed into a zero thickness layer that produces an appropriate resistance to the passage of heat. The model uses a simulation domain that matches the JEDEC standards for thermal testing.
The underlying PCB test board is also simulated, allowing STATS to simulate the effect of design modification. STATS can also include any type of heat sink that might be required by the customer.
Initial models are then correlated with corresponding experimental results from STATS' thermal database. Emigh explains, "This correlation involves making educated adjustments, based on experience and heat transfer expertise, to the properties and geometry of the simplified cuboids until the results are within 2% of the experimental data. The design details — die size, ambient temperature, power dissipation, etc. — are then modified to match the preliminary details of the customer design." Using this process, engineers at STATS have consistently obtained results that are accurate to within 5% of the actual thermal resistance determined by subsequent testing of the final devices.
"Initial simulation results, generally available within one or two days of receiving initial design information, are used to verify that the proposed package type meets the needs of a project," said Emigh. "If a thermal problem exists, it will have been identified very early in the design process so appropriate changes can be made. — P.B.
This thermal behavior of a stacked die was simulated from a customer's basic package design requirements before committing the design to production.
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Compound semiconductor removal: How to meet regulations
The explosive growth of the telecommunications and optoelectronics industries has greatly increased the use of compound semiconductor materials. Viable treatment and removal of contaminants from compound-semiconductor fab operations requires some familiarity with the aqueous chemistry of III-V elements (i.e., GaAs) on the periodic table. This knowledge will enable foundries and fabs to comply with local discharge limits and EPA regulations. See "Chemistry and treatment of III-V semiconductor wastewater," on p. 79 for more details.