Laser marking study proves benefits of simulation for backend tools
08/01/2001
Yoon S. Chang, Institute of Manufacturing, University of Cambridge, Cambridge, United Kingdom
Viji Krishnamurthy, John W. Fowler, Jong Mou, Department of Industrial Engineering, Arizona State University, Tempe, Arizona
Richard Kim, OHost Inc., Tempe, Arizona
overview
Researchers have developed a simulation model for an integrated laser marking machine and studied the effect of changes in a key system component on the manufacturing performance of the machine. The broader benefit from this work, specific to an integrated laser marking system, is that discrete event simulation is the best method for identifying the most effective settings in a specific manufacturing environment.
Integrating several wafer processing steps into one manufacturing system or "cluster tool" is desirable because it provides productivity and efficiency advantages. Advantages include reduction in the number of systems;, savings in cycle time, labor costs, and inventory; and, often, dramatic opportunity for yield improvement by preventing contamination. However, some integration concepts have shown disappointing production performance because interactions between process chambers, wafer storage, and transportation mechanisms were poorly understood.
While many researchers have analyzed cluster tools for wafer fabrication, few have looked at tool integration for assembly — semiconductor manufacturing's "backend" (see "Learning from past research").
To address this, we set out to design a simulation model that analyzed manufacturing performance of an integrated laser marking system. We wanted to use the model to study the effect of input tray size on cycle time and throughput. Further, we wanted to test and validate the effect of different internal transportation system configurations on the cycle time and throughput using the simulation model.
Modeling the integrated system
The target of our study was an integrated system designed to perform a number of sequential process steps, including input vision (V1), laser marking (L), and output vision (V2). V2 is advanced automated visual inspection. Within this system, tray-to-tray handlers automatically index and mark up to 30 trays of ICs with minimal operator intervention and setup time (see "The integrated system" on p. 88).
 Figure 1. Processing activities of a 4-by-8 tray. Black boxes represent active V1, L, and V2 operations. |
We took a two-step approach to analysis. First, we analyzed the activities of each system component. Second, we built a discrete event simulation model of the system and experimentally validated the model with real processing data. We used the simulation package "Extend" because it provided ease in simulating real time control processes [8]; Extend used MODL programming language, which is very similar to C. Discrete event simulation is helpful in incorporating the impact of randomness, such as component failures, into the model.
Estimation of cycle time
We determined the sequence of operations for a tray from its size and the time gaps between V1, V2 and L. For example, Fig. 1 shows an operation where a four-row by eight-column IC carrier ("tray") moves through V1, L and V2 with two sequence gaps between each operation.
The ideal situation is one with no failures and no rework. Theoretical cycle time for our analysis above can be calculated by adding the processing time of each stage in the sequence, index times, and times for pusher and tweezer at load and offload. Where simultaneous actions take place (i.e., V1 and L at the same time, as in row 4 of Fig. 1, for example), we used the longest process time of the two or three occurring at the same time.
Using this sequence and analysis, we determined an equation that estimated cycle time performance. This equation can be used to approximate cycle time and select tray sizes without simulation:
 |
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where (all times in msec):
Th = theoretical cycle time for a tray,
Ut = time taken by the load elevator to transfer a tray from the load carrier to the load elevator,
UPt = pushing and tweezing times on the load end,
V1,t = image capture time plus V1 process time,
Lt = laser process time,
V2,t = image capture time plus V2 process time,
ncol = columns on a tray,
nrow = rows on a tray,
gv1,L = gap between V1 and L (i.e., number of transport index moves),
gL,V2 = gap between L and V2,
Ot = time taken by offload elevator to transfer a tray from the offload carrier to the offload elevator,
OPt = pushing and tweezing time at offload,
Iv1 = index time for V1 (IV2 = index time for V2),
Iv1,L = index time for simultaneous operations V1 and L
(IL,V2 = L and V2), and
Iv1,L,V2 = index time for V1, L, and V2.
The equation indicates that the estimated cycle time of the system is influenced by a number of factors. In particular, it is dependent on the number of columns and rows of a carrier size as well as processing time of each process. As indicated in the equation, the first row of vision process does not require indexing.
 Figure 2. Cycle time/tray size vs. different tray densities. |
Experimental results
When examining examples of processing data and simulation conditions, it is obvious (see table) that load and offload, transport, push and tweeze, and V2 image process times are key contributors to cycle time. Among these factors, reduction of the V2 image processing time is dependent on the development of an advanced image processing algorithm, and reductions in load and offload elevator times depend on faster mechanical operations. Neither of these was within the scope of our research. Instead, we focused on factors such as transport time and tray size.
Our analysis yielded measures of cycle time (Fig. 2) and throughput (Fig. 3) performances versus different tray sizes. Our data showed that the 4-by-10 tray has poorer cycle time performance than the 4-by-8 tray, but achieves better throughput because of its higher density of ICs (units). A case of 588 4-by-8 trays holds 18,816 units and a case of 518 4-by-10 trays holds 20,720 units.
 Figure 3. Throughput for different tray densities for "Case B" in Fig. 2. |
Our results for cycle time from simulation test were consistent with those predicted by our equation. However, we found that by increasing the density of a tray, we could achieve better throughput. We also noted that even though tray content gives the same tray density, cycle time and throughput results vary. The cycle time differences are easily explained by our equation because row and column processing times affect tray cycle time. As in Fig. 3, when the density is the same (e.g., 4-by-12 and 6-by-8 trays), we should choose a tray size with a lower estimated cycle time from our equation to achieve better throughput and cycle time.
 Figure 4. Evaluation of tray transportation systems. |
We also looked at the effect of the transportation system on cycle time and throughput performance. The manufacturer of the tray transportation subsystem (i.e., a "one-tray transportation system") used on the system assumed that wait time between the upload elevator and the pusher and tweezer could be ignored and might not impact cycle time performance. The company based this assumption on the fact that these times were very small. However, we found that this wait time had significant impact on the cycle time.
Subsequent design of a new bi-directional transportation subsystem (i.e., a "two-tray transportation system") helped to improve throughput by >50% compared to the previous system (Fig. 4). In addition, the new system reduced cycle time by 22%.
Conclusion
Our work was specific to an integrated laser marking system where we developed an equation that helped us approximate cycle time performance for given process. However, we found that discrete event simulation is the most effective method for identifying the most effective settings (i.e., tray size, tray density, transportation system, etc.) in a specific manufacturing environment.
References
- T. Perkinson, P. McLarty, R. Gyuresik, "Single-Wafer Cluster Tool Performance: An Analysis of the Effects of Redundunt Chambers and Revisitation Sequences on Throughput," IEEE Transactions on Semiconductor Manufacturing, Vol. 9, No. 3, pp. 384-400.
- S. Venkatesh, et al., "A State-State Throughput Analysis of Cluster Tools: Dual-Blade Versus Single-Blade Robot," IEEE Transactions on Semiconductor Manufacturing, Vol. 10, No. 4, pp. 418-424.
- S.C. Wood, "Cost and Cycle Time Performance of Fabs Based on Integrated Single-Wafer Processing," IEEE Transactions on Semiconductor Manufacturing, Vol. 10, No 1, pp. 98-111.
- S. Wood, "Simple Performance Models for Integrated Processing Models," IEEE Transactions on Semiconductor Manufacturing, Vol. 9, No. 3, pp. 320-328.
- N. Pierce, M. Drevna, "Development of Generic Simulation Models to Evaluate Wafer Fabrication Cluster Tools," Proc. of Winter Simulation Conference, pp. 874-878, 1992.
- R. Hendrickson, "Optimizing Cluster Tool Throughput," Solid State Technology, July 1997, pp. 217-222.
- J. Mauer, R. Schelasin, "Using Simulation to Analyze Integrated Tool Performance in Semiconductor Manufacturing," Microelectronic Engineering, Vol. 25, pp. 139-146.
- Imagine That Inc., Extend Manual, 1995.
Yoon S. Chang received his doctoral degree in mechanical engineering from Imperial College, Science, Technology and Medicine, at the University of London, United Kingdom. Chang is a senior industrial fellow in the Institute of Manufacturing at University of Cambridge, Mill Lane, Cambridge, CB2 1RX, UK; ph 44/1223-766-141, fax 44/1223-338076, email [email protected].
Viji Krishnamurthy earned her MS in industrial engineering from Arizona State University. Krishnamurthy is now a PhD student at Northwestern University.
John W. Fowler received his PhD in industrial engineering from Texas A&M University. Fowler is an associate professor in the Industrial Engineering Department and is co-director of the Modeling and Analysis of Semiconductor Manufacturing Laboratory at Arizona State University.
Jong-I Mou earned his BSME and MSME from the University of Wisconsin-Madison and his PhD from Purdue University. Mou is an associate professor at Arizona State University.
Richard C. Kim received his BS in electrical engineering and computer science from the University of California at Berkeley and his PhD in electrical engineering from the University of Minnesota. Kim is the founder and president of OHost Corp.
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Learning from past research
Currently, analytical modeling and discrete event simulation are the most common approaches in the analysis of integrated system. For example, one research group has shown that, when using a single-blade robot for wafer handling, redundant chambers and revisiting schedules can increase the performance-cost ratio of cluster-based fabrications, making them more attractive [1]. Redundant chambers improve the performance of the cluster tool when a chamber's processing time is significantly longer than that of other chambers on the tool. The trade-off for this increase in performance is the cost of including extra chambers in the design. Revisiting a chamber allows a greater number of process steps to be handled without the need and expense of adding extra chambers.
Another group studied cluster tool throughput when using a dual-blade robot for wafer handling [2], extending the information outlined above. They defined two types of schedule: transport-bound and process-bound. According to their research, the dual-blade robot improves the throughput of the cluster tool over a single-blade tool under a process-bound condition. Under transport-bound conditions, the throughput of the cluster tool is the same for both dual-blade and single-blade tools.
Other work has shown that in some cases lot size reduction can actually decrease maximum tool throughput [3]. Some process tools require setups or other overhead time that is independent of lot size. As the lot size decreases, such overhead occupies an increasing fraction of a tool's total time spent processing lots, which reduces the tool's maximum achievable throughput. Thus, the tool's maximum throughput rate decreases if the lot size falls below a certain threshold. When the lot size falls below this threshold, additional integrated tools would be required to maintain the original throughput rate. This threshold becomes higher (i.e., larger lots sizes are required) as the total module processing time in the integrated tool decreases or the number of modules/integrated tool increases.
Yet other work has shown that throughput time within a cluster tool can be approximated as T + lt, where T is the fixed throughput time of cluster, l is the lot size, and t is the average incremental throughput time resulting from a lot size increase of one wafer [4]. This model predicts an increase in a cluster's throughput rate of 10% over current operating practice if one lot can be loaded while a different lot is being processed.
Since integrated tools can often handle multiple cassettes that have independent arrival times, the calculation of tool parameters is non-trivial. Because of this asynchronous behavior, the throughput is no longer inversely related to cycle time. Jobs interfere with each other. Engineering research has developed generic simulation models for wafer fabrication cluster tools that enable users to analyze multiple processes using different dedicated chambers, multiple processes using the same chamber, and a single process with multiple chambers [5].
One useful piece of work presents a throughput predictor model for quick simulation of various tool scenarios with a range of variables [6]. Using this model, throughput analysis that generally takes days or weeks to perform using a spreadsheet now only takes hours. The results can be used to guide the design of a new cluster tool and the optimization of throughput gains. This work classified factors affecting throughput into three areas: factory interface cycle, process cycle and pipeline crossover cycle.
Finally, we found instructive work that developed a simulation model for a case where traditional tool planning methods were proven to be inadequate [7]. This work showed that simulation is required not only to assess the impact of changes in the tool, but also for changes in line loading and process sequence.
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The integrated system
Upload elevator: A tray of packaged integrated circuits is loaded onto a carrier on the upload elevator end. The upload elevator raises and separates a tray from the carrier and waits for the transport to load the tray.
Pusher and tweezer: On the upload end, the pusher pushes the tray from the upload elevator to the transporter and the tweezer places the tray exactly on the transport. Then the tray is clamped on the transporter. On the offload end, the pusher moves the tray from the transporter to the offload elevator and the tweezer places the tray exactly on the offload elevator. Then the tray is clamped on the offload elevator.
Transporter: The transporter moves the tray from the upload end to the offload end of the machine. A computer controls its position, time of movement, move times and move distance.
Vision-1 process: The Vision-1 process inspects the presence and position of packages on a tray. It consists of two stages: image capture and image process. Two cameras are used for capturing images and the information is sent to a computer for Vision-1 process control. The computer processes the images and determines the available number of packages and their positions and relays the information to the computer that controls the laser process to decide the proper laser marking time.
Laser marking process: The laser computer decides the marking time from the Vision-1 computer's output and all packages in a column are marked at same time.
Vision-2 process: The Vision-2 process evaluates the quality of laser marking. It also consists of two stages: image capture and image process. Two cameras are used for capturing images and the information is sent to the computer. The computer processes the images and evaluates the laser mark.
Offload elevator: The Offload elevator raises the semiconductor package tray and clamps it on the offload carrier.