Technology News
07/01/2001
New bonding technology zips fabrics into 3-D circuits
Semiconductor startup Ziptronix Inc., Research Triangle Park, NC, has developed a revolutionary and widely applicable 3-D wafer-scale integration and interconnect technology that allows for stacking fabrics (Fig. 1).
Increasingly used, "fabric" refers to a semiconductor material or function. The International Technology Roadmap for Semiconductors, for example, refers to various system-in-a-package functions as fabrics. Within the context of Ziptronix's new technology, fabric refers to the stacking of dissimilar semiconductor materials, logic, memory, etc.
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Figure 1. Ziptronix's bonding and interconnect technology enables 3-D packaging of dissimilar semiconductor fabrics, thus achieving orders-of -magnitude performance gains.
While much of the work is proprietary, Ziptronix outlined for Solid State Technology how the process starts with a host wafer containing many chips. Then, other wafers or individual chips are bonded to the host at room temperature, via true covalent bonds between the two bonded materials. The substrate from the second wafer or individual chips is then removed (using grinding or chemical mechanical polishing), leaving only a few microns containing the active electronics. Electrical interconnects between layers are then made between the host and the bonded wafer or die using a standard via-based interconnect process identical to the process routinely used in semiconductor manufacturing.
A high degree of perfection is obtained in the Ziptronix wafer bonding process (Fig. 2). Bob Markunas, Ziptronix co-founder and VP of marketing, says, "The bond is so strong that when a mechanical wedge is forced between layers, the carrier substrate for a given layer will fracture before the interface will separate."
"The process can be repeated multiple times. The end result is integration of many chips into a single three-dimensional structure, providing orders-of-magnitude performance enhancements over today's two-dimensional chips," says Markunas.
While the stacking concept is not revolutionary, Ziptronix's technology involves an elegantly simple approach. It uses proprietary but rudimentary surface preparation based on standard processes and materials available in today's high-volume wafer fabrication facilities, to create and interconnect stacked fabric structures, even nonsemiconductor fabrics (e.g., hi-Q passives ground layers, or thermal spreaders).
"This is done at room temperature to eliminate thermal stress, knocking down the most significant road block to previous fabric-bonding approaches. We don't use any exotic materials to bond the fabrics; we only use each fabric's natural desire to bond with its neighbor. Monolayer termination of the surfaces prior to bonding is used to control their passivity to normal fab ambient and their mutual reactivity on contact," says Markunas.
 Figure 2. A high-resolution transmission electron micrograph that shows a room temperature wafer bond interface between silicon and indium phosphide wafers. |
Re-routing layers can be added, but are not necessary. Markunas says, "We see two applications: one in which devices are bonded and interconnected at the pad level — for example, memory onto a large logic device where the memory die is much smaller than the logic die. In this case, no routing layer is required on existing chips and is only added after bonding for pad interconnection. In the other case, devices are designed specifically to take advantage of the Ziptronix process. In this case, interconnect layers can be added for optimum performance. We even envision a generic interface being defined so designers can fabricate components to allow for end process mixing and matching of functionality."
Once interconnection is complete, the wafers are sawed and packaged. Since the bonded fabrics are thinned, leaving only a few microns of material on carrier die, the end structure can be placed in standard packages. "An additional advantage with this technology is that, in many cases, I/O drivers and associated pins can be removed reducing overall power consumption and cost associated with those pins," says Markunas.
The resulting products consume less power, run faster, cost less, and consume less space. And since the process uses existing, standard industry equipment and techniques, the Ziptronix approach is inherently a repeatable manufacturing process.
Marcunas says, "Potential applications include single chip cell phones with integrated Bluetooth technology, higher speed wireless LANs, lower cost 3rd-generation wireless base stations and significantly higher bandwidth optical network components."
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Little silicon mirrors enable "light speed" Internet
A fascinating silicon chip is at the heart of an emerging trans-Atlantic optical network that will change our expectations for data service and speed. It's Murray Hill, NJ-headquartered Lucent Technologies' MicroStar technology — 256 mirrors fabricated on one square inch of silicon (see photograph).
With sophisticated software control, these tiny micro-mechanical mirrors are tilted to reflect individual wavelengths from an incoming cable fiber to an outgoing fiber route, thus eliminating the slow and power-consuming conversion to electrical signals in today's long-haul networks.
 A Bell Labs scientist tests one of the 256 micro-mirrors on a WaveStar LambdaRouter chip. Each mirror is about as wide as the eye of a standard sewing needle. |
Without needing optical-electrical-optical conversion, this compact switch provides more than 32x greater switching density, 16x faster than today's best electronics switches used in communications networks. In simple terms, they can route two billion one-page e-mail messages per second.
MicroStar is at the heart of Lucent's LambdaRouter, which provides up to a 100-fold reduction in power consumption over electronic solutions. The first commercial use of WaveStar LambdaRouter is emerging in Hamilton, Bermuda-based Global Crossing's multi-cable, transatlantic optical network, which is connecting routers in the US and Europe. This will be the world's first high-capacity, all-optical switch for communications networks. Router installation will be completed in 3Q01.
The router, which acts like an optical traffic cop, will enable Global Crossing to route up to 10 Tbit (trillion bits) of information/second. Lucent's routing software will enable the all-optical switches to communicate with one another, instantly discover new switches and links as they are added to a network's topology, and automatically redistribute wavelengths in response to fluctuating traffic demands and network resources.
Wally Dawson, executive VP of Global Crossing's global network, says, "Lucent's LambdaRouter provides our Atlantic mesh network with improved speed, reliability and failure protection." Mesh protection is an engineering approach that protects transmission of data traffic by allotting reserve optical capacity within the existing multi-cable network in case of downtime on one or more of the optical cables.
Gerry Butters, president of Lucent's Optical Networking Group, says, "Optical wavelengths are the true building blocks of next-generation networks. They will deliver vast amounts of information literally at the speed of light, unimpeded by the bottlenecks of conventional transport systems."
In just one applications example, optical networking will give a local service provider the ability to provide HDTV-quality video conference between Silicon Valley and London at a moment's notice — a virtual fiber link between the two locations with a direct connection from point to point. The same task, without an all-optical link, would typically require a carrier to patch together a series of digital switches, which would take several hours and considerably more network and staff resources.
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Method for step-free semiconductor surfaces
Researchers at NASA's Glenn Research Center, Cleveland, OH, have received a second patent for their method of growing atomically flat surfaces — without a single step even one atom high (see figure) — on commercial semiconductor wafers. While the patents cover silicon, silicon carbide (SiC), and III-V semiconductors, to date the Glenn research group has only demonstrated the process with SiC.
Researcher Phil Neudeck says, "We've demonstrated this over 50mm diameter SiC wafers, which is the largest size of SiC wafer that our epitaxial growth system can accommodate." The largest currently commercially available SiC wafers are 75mm, which have just recently been introduced onto the market.
Such step-free surfaces could help improve the performance and reliability of ICs fabricated for a wide variety of applications. Despite their polished surface, conventional commercial semiconductor wafers are covered with steps, typically one to eight atoms high, on both virgin and processed wafers.
The Glenn research team makes step-free surfaces by first etching device-sized arrays of mesas into wafers. Next, by controlling conditions, the researchers limit crystal growth to the riser, or side, of each atomic step. The CVD process is done in a commercial epitaxial system. The crystal at each step grows sideways until the step reaches the edge of the mesa, leaving behind an atomically flat surface.
Tony Powell, senior research physicist at Glenn, says, "We've flattened silicon carbide mesas as large as 0.4 x 0.4mm and, depending on the mesa size, over half of the mesas on a wafer." What results is a wafer full of individual IC-sized areas that are step-free.
"What's so attractive about our method is that, with just one extra patterning step in the fabrication, manufacturers can make these step-free surfaces," Powell says. The researchers equate the cost for this processing as simply "the cost for one additional photolithography, etch and epitaxy process sequence for a particular device process in a given facility."
Mesas not made flat contain screw dislocation defects — so called because of the warped spiral stacking of the crystalline planes — which are not amenable to this flattening method. "For SiC, the substrate defects are the primary limiting factor right now," says Neudeck.
Standard percent yield vs. defect density and device area statistics apply. Compared to silicon, SiC is a relatively immature substrate material that typically contains on the order of 104 screw dislocations/cm2, so yields drop off sharply after the mesa size grows larger than 10-4 cm2.
 Comparison of (left) conventional rough SiC and (right) a SiC surface rendered atomically flat by a sequence of process steps developed at NASA Glenn Research Center. |
"When mesa sizes are kept well below 10-4 cm2, the process can be carried out with high yield over nearly all of a 50mm SiC wafer," says Neudeck. "Based on an expected small, non-zero, rate of nucleation, we expect there will be a mesa size limit to this process. However, the defects present in commercial SiC wafers have precluded us from quantifying this potential limiting factor at this time." He notes that these limits will change for different materials, epitaxial processes, and mesa sizes. An added benefit of the method is that it isolates the screw defects into mesas that can be identified and avoided.
Studies by other scientists have linked surface steps in the wafer to defects in semiconductor films that are different from the wafer material. The defects cause poor performance and reliability and have been troublesome to the development of new electronics for aerospace applications.
"We believe that step-free surfaces will enable remarkable improvements in devices based on silicon carbide and gallium nitride. These are the materials of choice for making high-power solid-state switches as well as electronics for hostile environments, such as pollution and noise control devices inside aircraft engines," Powell says. All experiments to date have been mesas etched into SiC substrates.
Industry researchers are using these materials for blue light emitting diodes for lighting, blue lasers for higher capacity DVDs and high efficiency transistors for more reliable electrical power switching and improved wireless communications. Glenn Research Center conducts instrumentation and controls research on sensors, electronics, photonics and microelectromechanical systems for aeronautics and space applications.
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Oak Ridge, Motorola, Pacific Northwest agree to pursue new materials
Scientists at Oak Ridge National Laboratory (ORNL), Motorola Labs, and Pacific Northwest National Laboratory (PNNL) have entered a cooperative research and development agreement to study new materials that will increase the speed of future generations of integrated circuits. The new materials may overcome a fundamental physics problem that threatens to limit future semiconductor improvements, for which the semiconductor industry currently has no solution.
The industry has relied predominantly on geometry shrinks to produce smaller, faster, and better electronic devices. However, physical limitations will eventually prevent semiconductor designers from achieving additional reductions. The problem lies with the current gate insulating material, a layer of silicon dioxide approximately 35Å thick, the thickness of 25 individual silicon atoms. The insulating layer "gates" the electrons, controlling the flow of electricity across the transistor. Each time chip geometries are reduced, the SiO2 layer must also be proportionally thinned. At the current pace, industry experts expect necessary gate thicknesses to be fewer than 10Å in the next 10 years. However, once the thickness is <20Å, as anticipated later next year, the SiO2 layer thickness will be in a range where quantum tunneling effects become an issue. At this juncture, most industry experts see the need for new materials with higher dielectric constants and materials that have a higher capacitance for a given thickness.
Independently, ORNL and Motorola Labs have been developing high-k materials in the form of crystalline oxides on silicon and other semiconductor materials. Motorola, for example, has demonstrated the world's thinnest functional transistor with electrical properties more than 10 times better than equivalent SiO2 using a strontium titanate crystalline material on a silicon substrate. Scientists in both labs anticipate their combined expertise will enable them to solve the remaining issues more quickly.
The three-year research agreement has two phases. The first phase transfers the details of ORNL's patented crystalline oxide on silicon process to Motorola Labs and PNNL. The second phase tests and optimizes the technology to ensure that critical performance and processing issues required for aggressive scaled alternative gate silicon technology can be met. Motorola Labs will evaluate the technology with some plans to tailor the technology to Motorola-specific needs.
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Polycrystalline-diamond yields thermally driven solar cells
Researchers at Vanderbilt University, Nashville, TN, have built a theoretical case for the efficiency and applicability of polycrystalline-diamond for thermally driven solar cells in space applications, replacing silicon solar cells used in many space missions.
Now, with a $348,000 grant from the DOD's National Reconnaissance Office (US government spaceborne reconnaissance), Timothy Fisher (Fig. 1), assistant professor of mechanical engineering, and Weng Poo Kang, an associate professor of electrical engineering and computer science, are beginning work to prove the theory.
According to Fisher, diamond has a number of potential advantages for use in outer space, including the ability to withstand the high levels of radiation typical of space environment. Currently, the performance of silicon cells degrades ~50% after 10 years in orbit, but no degradation is expected with diamond.
In addition, diamond solar cells will be able to operate at high temperatures, enabling concentration of solar energy onto the diamond cell; in use, the compact diamond converter will be used with an inflatable, lightweight concentrator. "As a result, they can be used with low-weight inflatable solar collectors, resulting in an energy system that produces more electricity per pound, a critical factor in space applications," says Fisher. Perhaps their most impressive attribute, diamond solar cells have a potential conversion efficiency of ~50% compared to 10-15% for silicon solar cells. This also makes them desirable for land-based applications.
Fisher estimates that diamond solar cells will not be much more expensive to mass produce than silicon solar cells. "In large volumes, using chemical vapor deposition from methane, you should be able to make this material for about $1/cm2," he says.
So far, the advantages and costs of diamond solar systems are largely theoretical. No one has tried to make a diamond solar converter before. Fisher got the idea from the research of Vanderbilt colleagues Kang and
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Figure 2. Within a diamond-based solar-electric converter, concentrated sunlight is focused on a radiation absorber heating it to ~1000?C. The device's gate layers produce an electric field that pulls larger numbers of electrons off the heated diamond tip cathodes (see insert, which shows microscopic diamond pyramids at ~10 million/cm2). These electrons flow through a vacuum to reach the anode, producing an electric current. (Source: Timothy Fisher)
"Diamond" Jim Davidson, professor of electrical engineering, who have been studying the use of polycrystalline diamond for electronics and sensor applications for a number of years. Applications include high-temperature oxygen sensors, capacitors, and ion neutralizers, among others.
"When I saw that they had found diamond film emits electrons efficiently — you don't have to use strong electric fields and a lot of energy to pull them from the surface — I realized that it could be used for energy conversion. The concept is not new, but the application to energy conversion is," Fisher says.
His diamond solar converters are not photovoltaic devices (converting light directly into electricity) like silicon cells, but nanoscale solar thermal devices that convert light into heat and heat into electricity (Fig. 2). Fisher explains, "Diamond solar cells are very similar to thermionic emission devices that were developed more than 40 years ago. In fact, they are a close cousin to vacuum tubes. In thermionic devices, electrons are released by heating. In diamond devices, however, electrons are extracted by combining heating and an electric field (Fig. 2).
"It is this nanoscale physics that makes the device work," Fisher says. "It creates a large amount of current and a small voltage. Voltage can then be increased, in a straightforward manner, with a DC-to-DC converter that increases the voltage and reduces the current. This can be done with about 90% efficiency."
Fisher and his colleagues have been working on a small test device with a plain diamond film without the pyramids. "What we have seen increases our confidence that the converter will work," he says. The goal of the nine-month project, which is also partially supported by a National Science Foundation Career award, is to produce a prototype cell that is a square centimeter in size and produces 10W of electrical power at 1000°C. — P.B.
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Kodak furthers licensing of OLED technology
Opsys, Oxford, UK, has become the first European licensee of Eastman Kodak Co.'s organic light-emitting diode (OLED) technology. The licensing agreement grants nonexclusive rights to Kodak's small-molecule OLED technology, including manufacturing processes and device structures for passive monochrome and color displays.
 Unlike traditional LCDs (right), OLEDs (left) are self-luminous, which eliminates the need for backlighting and allows for thinner, more compact displays. |
OLED technology, also referred to as organic electroluminescence (OEL), is a self-luminous display technology based on thin organic films that emit light when stimulated with an electrical charge. Unlike traditional liquid-crystal displays (LCDs), no backlighting is needed, eliminating bulky and environmentally undesirable mercury lamps. The result is thinner, more compact displays (see figure). The emitted light can be individual colors of red, green or blue, or they can be combined to create full-color, high-resolution image displays. OLEDs have a wide viewing angle (up to 160°), even in bright light. Their low power consumption, 2-10 V, provides good efficiency, and helps minimize heat and electrical interference in electronic devices.
The OLED cell structure is made up of a stack of thin organic layers sandwiched between a transparent anode and a metallic cathode. The organic stack is composed of four layers: a hole-injection layer, a hole-transport layer, an emissive layer, and an electron-transport layer. The organic materials may include "small" molecules deposited through vapor sublimation in a vacuum chamber, or "macro" polymers, often deposited with solvent coating
techniques. When an appropriate voltage, typically a few volts, is applied to the cell, injected positive and negative charges recombine in the emissive layer, producing electroluminescence. The structure of the organic layers and the choice of anode and cathode are designed to maximize the recombination process in the emissive layer, thus maximizing the light output. Enhancement of electroluminescence efficiency and control of color output can be achieved by "doping" the emissive layer with a small amount of highly fluorescent molecules, critical in producing color OLED displays.
OLEDs can be active- or passive-matrix displays. Low-cost and low-information-content applications such as alphanumeric displays typically use passive-matrix displays, which connect an array of pixels at intersecting anode and cathode lines. To simplify fabrication, making it adaptable to large-area, high-throughput manufacturing, Kodak uses a "rib" (also called a base or pillar) structure pre-formed on patterned ITO anode lines. When the organic materials and cathode metal are deposited, the rib structure provides the desired electrical isolation for the cathode lines. In contrast, an active-matrix OLED has an integrated electronic backplane as its substrate and lends itself to high-resolution, high-information-content applications including video and graphics. Using polysilicon technology, thin-film-transistors (TFT) with high-current carrying capabilities and high switching speeds are possible.
OLED technology may be able to increase the versatility of flat panel displays ranging from thinner and lighter handheld devices to wall-mountable television systems. Opsys will use the technology to manufacture 1- to 5-in. diagonal displays for portable communications devices, such as cell phones, pagers, and PDAs. The agreement will help drive the growth of information imaging, a $225 billion market uniting three closely related imaging markets — devices, infrastructure, and services/media.
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Intel chip boasts low energy, high processing for wireless
Intel, Santa Clara, CA, has unveiled an experimental computer chip based on a new process technology that combines the core components of today's cellular phones and handheld computers.
This integrated, "wireless-Internet-on-a-chip" technology, shown at the Intel Developer Forum in Amsterdam, could enable a new era of wireless Internet-access products with extensive battery life and greater processing power, according to the chipmaker.
Intel said the new research chips feature logic (microprocessor), flash memory and analog communications circuits on a single piece of silicon built using a single manufacturing process. Each of these types of circuits is traditionally manufactured on separate process technologies in different factories. Chips produced by the new process may be up to five times more powerful than those used in today's cell phones, capable of operating at speeds of up to 1 GHz and providing up to a month of battery life, according to Intel.
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Flip chips on leadframes for fast apps
Amkor Technology, Chandler, AZ, has developed flip-chip-to-leadframe packaging (see drawing) that beats wire bonding for high-frequency performance in 5-20GHz applications. This is the industry's first combination of an 8-mil leadframe and 200µm ball-pitch flip chips.
By its nature, this new package features a very short interconnect distance between die bump pads and a motherboard, resulting in reduced insertion loss, inductance and parasitics.
An Amkor spokesperson told Solid State Technology, "Today, direct-attach flip-chip is generally limited to products such as wristwatches that have tight size constraints. For products with larger system boards, there are two economic factors, both related to pad pitch, that make flip-chip in-package desirable. One is the cost of assembly equipment with the necessary placement precision required for direct attach. The other is the cost of high-density circuit-board material itself — you can't space the bond pads on conventional board material closely enough to match the pad pitch on the chip. In area-array packages, flip-chip in-package reduces the number of square inches of high-density substrate needed. With our new fcMLF technology, it's even better; you don't need any high-density material because you're down to an inexpensive leadframe."
The design allows package engineers to place large die in a smaller than normal footprint because there is no periphery space needed for wire bonding. While the initial package offering incorporates flip chip with the micro leadframe design, Amkor expects to adapt additional packages to the flip chip leadframe form factor.
These packages are expected to be in demand for applications requiring a frequency range of 5-20GHz and lead counts of less than 100 I/O. These applications include controllers, power amplifiers and other communication devices needed for high-frequency networks or wireless applications.
Two alpha customers will begin receiving fcMLF packages in May 2001 for evaluation. High-volume manufacturing is expected to begin during 4Q01.
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New front or back IC failure analysis technique
An engineer at Sandia National Laboratories, Albuquerque, NM, has developed an optical beam failure analysis (FA) technique that quickly detects IC defects from both the front and back of the device. The technique combines thermally induced voltage alteration (TIVA) and Seebeck effect imaging (SEI). TIVA SEI finds failures in ICs as fast or faster than any previously used techniques.
The work is that of Ed Cole, a distinguished member of Sandia's technical staff, who in the mid-1990s co-invented TIVA's older "cousins" charge-induced voltage alteration (CIVA) and light-induced voltage alteration (LIVA). Cole says, "CIVA was the first induced voltage alteration FA technique developed at Sandia. It localized open conductors using a scanned electron beam. LIVA uses photocurrents produced with relatively short wavelength light. The new method, TIVA, uses heat."
 Amkor's new flip chip on MicroLeadFrame (fcMLF) package was designed for high-frequency applications; it provides electrical performance superior to wire bond packages. |
Briefly described, with TIVA, a focused infrared laser bean, operating at wavelengths for which silicon is transparent, heats only a small part of an IC at a time. The localized heating produces a voltage change that is biased with a constant current source. An image of the circuit's response is generated by rastering the laser spot over the circuit with a laser-scanning microscope while recording changes in the power requirements. The laser-scanning optics also generate a reflected light image that when registered with the TIVA image allows for rapid localization of any failures detected.
Cole explains, "Faults and failures within a circuit react differently to heat stimulation than operational components. In an unflawed device, the effects produced by the heat don't change the circuit's operation. However, if the power demands of the chip change due to the local heating, it is an indication of flaws. The SEI mode detects if a conductor is open, while TIVA locates a short circuit."
Cole goes on to say, "TIVA is extremely sensitive and allows us to see flaws we either couldn't detect before or could locate only with significant time and effort."
One of the significant aspects of TIVA is that it allows for scanning of the IC from both the front and back. "This is important because state-of-the-art chips employ up to seven layers of metal interconnections, preventing direct observation of deeper structures from the front of the device," Cole says. "In addition, flip-chip or upside down packaging denies direct access to the front surface. TIVA gives the ability to evaluate the IC from both sides." TIVA has also been successfully applied to diagnosing various failures in MEMS.
Sandia has licensed LIVA and TIVA/SEI to OptoMetrix Inc., Seattle, WA, an optical instrumentation company specializing in IC FA. The license allows the company to market equipment using the technologies. This is the first time an equipment manufacturer has licensed them for sale.
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SoC market — bulletproof?
Driven by a rising tide of demand from the communications world, SoC shipments so far this year are 17% ahead of shipments made at the same time last year. This month's Market Watch predicts that when 2002 rolls around, SoC dollar shipments to the Americas and Japan will grow nearly a third over the previous year. See the full story on p. 58.
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Copper good well into next decade
Engineers at Infineon Technologies Munich Corporate Research Labs have demonstrated that present techniques for IC wiring can be used well into 2011 to 2014, the current end of the International Technology Roadmap for Semiconductors. They have produced 40-50nm copper (Cu) metal lines using damascene processing (see illustration) and proven electrical performance.
 Significant 40-50nm copper metal lines done by engineers at Infineon Technologies' Corporate Research Lab. |
The wafer processing for these tests was done at International Sematech, Austin, Texas, using semiconductor manufacturing equipment and processes developed for 250nm feature sizes.
Electrical tests verified sufficiently low electrical resistance for all wire lengths relevant for future semiconductor manufacturing. The tests concluded that neither the fabrication of these lines nor the electrical resistance will be technical obstacles for the ongoing process of chip shrinking.
The group spokesperson told Solid State Technology, "This achievement demonstrates the extendibility of the damascene technique to realize advanced chip metallization."
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The future is now for step-and-flash imprint litho
A yet unheralded alternative for future lithography, step-and-flash imprint lithography, appears to be an inexpensive method for pattern generation capable of sub-100nm resolution on silicon wafers. Researchers at the University of Texas have shown that this process has several advantages over comparable compression imprinting techniques for applications that require precision layer-to-layer alignment error measurement. Development work has been so promising that commercialization is under way. See p. 67 for more details.
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Prototype EUV system completed
In the photo an engineer works with wafers from the first full-scale prototype extreme ultraviolet (EUV) lithography system — the Engineering Test Stand (ETS) — at Sandia National Laboratories in Livermore, CA, which was unveiled in April.
Chuck Gwyn, program manager of EUV LLC, says, "The completion of the prototype machine marks a major milestone for the program, since we have proven that EUV lithography works. Our next step is to transfer the technology to lithography equipment manufacturers to develop beta and production tools."
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The EUV ETS was developed by industry-government collaboration among three US Department of Energy national laboratories (i.e., the "Virtual National Laboratory") and EUV LLC, a consortium of semiconductor companies. EUV includes Intel, Motorola, AMD, Micron Technology, Infineon Technologies, and IBM. Using the EUV LLC, private industry has funded 100% of the EUV lithography research through an agreement that spans from 1997 through early 2002. The ETS will be used during the next year to refine the technology and get it ready to create a prototype commercial machine that meets industry requirements for high-volume chip production.