System-on-a-chip challenged by stacked system-in-a-package technology*
07/01/2001
System chip technology has hit a wall, and so has the system chip business. Indeed, some wonder if system chips may turn out to be just a niche market. Improving process technology usually means chip performance/unit cost roughly doubles every year, but the system chip has fallen off this curve. The technical problems of combining different processes on one chip mean the system chip lags behind the latest stand-alone versions of its individual components.
Compromises have to be made to combine the latest-generation low-voltage logic with high-voltage memory and analog devices. While the latest-generation logic and DRAMs may use 0.13µm processes, the flash memory or analog parts of the system chip still need 0.18µm or 0.25µm processes, so the whole system chip has to use that design rule.
"If we don't do something, the system LSI business will come to a standstill," says Hiroo Mochida, director of Rohm's LSI Development Systems Headquarters.
Customers making consumer products aren't keen on the high costs or long development time of system chips. Though chipmakers have promoted the chips as a custom product, high costs of design and process development, and all the expensive masks, have actually made chips too costly to be practical for small runs. "Running 100,000 units/month, it takes 2 to 3 years to recoup our investment, or about 3 million units," says Naoki Yashiki, assistant to the GM at Hitachi's Electronic Devices Sales & Marketing Group. That makes a system chip out of the question for the typical custom product run of 20,000 units/month.
Also consider how long it takes to develop one of these chips. Suppliers say it can take 1 to 2 years to devise a system chip that combines several different processes, including evaluation — not great news for the guts of a cell phone that changes models every six months.
But now new technology for stacking multiple chips into one package looks likely to solve all these problems. The system-in-a-package (SiP) can use the latest chips off the shelf, and is smaller, cheaper, and faster.
Unlike the old multichip modules, this latest generation of multichip packages usually stacks the chips vertically, using technologies developed over the last few years for the various new types of chip-sized packages, like flip-chip attachment. The experience with CSPs also made companies familiar with packaging chips made by other suppliers, and dealing with bare chips and known good die.
 SoC vs. SiP costs. SiP has increasing cost advantage at smaller geometries. Source: Matsushita |
The SiP drastically reduces development time and cost (see figure). By using existing chips, a sample package can usually be shipped within two months, though developing a new chip to combine with some off-the-shelf units might take six. Stacking the chips on top of each other instead of laying them out across the substrate can make the circuit lengths shorter than in a system chip, for faster performance and lower power consumption. Connecting two stacked chips directly with fine pitch bumps "can make circuit length the same as within a single chip," say Rohm engineers. And each chip in the unit can be the most advanced of its type, with no problems combining different processes with different voltages and design rules. Components can be upgraded without having to redesign the whole unit. And stacking the chips packs them into less board real estate.
Though systems-in-a-package now contain just active devices, they could also include passive components. Toshiba aims to make a SiP that includes passive components by 2002-03, combining all the functions for a mobile phone into one package.
While there may be growing agreement on the potential for the SiP, there's still no consensus on the best way to make the packages. There are currently four main competing approaches: chip-on-chip, chip stack, stacked packages, and direct attachment to the substrate.
The chip-on-chip packaging method flip-chip-attaches the top chip with bumps directly to the bottom chip, for the shortest connections and fastest speed. But only two chips can be connected, and care has to be taken not to damage the base chip. Rohm started mass-producing systems packages for PCs with this technology, turning out 3 million units/month this spring. Hitachi plans to start production with this method in September, and Matsushita, Mitsubishi, and Sony plan to do so by 4Q02.
The stacked chip package stacks chips on top of each other and wire-bonds them to each other and to a substrate. This type is already in production for multichip packages combining flash memory and SRAMs. Since the stacked chip package uses existing equipment, it's cheap and can be stacked with up to about four chips with reasonable yield. But the chips have to be of appropriate graduated sizes so one can be wire bonded to the next. Oki planned to start volume production of various two-chip units by this method this spring: first, logic combined with memory or radio frequency chips for audio applications, then units for games, phones and chip recorders. Sharp says it will mass-produce up to four-chip stacks by this process before year's end.
Also, the chips can be packaged first in ultra-thin packages, which can then be stacked vertically. This method can be used easily with different kinds of chips, and it simplifies testing. Relatively standard package technology holds down costs, but the wafers do have to be thinned down. Toshiba will use the approach in volume production starting in 3Q01, first stacking memory chips, then combining memory and logic.
Finally, chips can be attached separately to the substrate, whether by flip-chip bumps or wire bonding, most suitable for high-speed, high-pin-count devices. Passive components can be included. Hitachi has started shipping a RISC chip-and-memory unit, and is planning to produce other custom products. Fujitsu planned to produce cell phone and data communications adaptor chips in one package this spring.
Hiroshi Asakura is an editor at Nikkei Microdevices, 2-7-6 Hirakawacho, Chiyoda-ku, Tokyo 102-8622, Japan; ph 813/5210-8311, fax 813/5210-8530.
*This article has been translated for Solid State Technology from the March 2001 issue of Nikkei Microdevices, our partner in Japan.
____________________________
Chipmakers to compete with assembly houses for SiP
System-in-a-package puts the chipmakers in direct competition with the assembly houses that specialize in just this kind of technology. If a semiconductor company's own packaging division doesn't have technology that is significantly better, it might as well get out of the business.
Amkor Technology Inc. has been touting its technology to get around the limitations of system chips for some time, with its systems packages that combine both multiple chips and passive components in one unit. The company is already producing some 750,000 SiPs/month, for high-frequency telecommunications and memory applications. It works with the electronic systems designers and the chip designers — not with the chipmakers' packaging group — to come up with a package. Sources at Amkor Technology Japan claim the package specialist has a big advantage in technology and cost. Thus, the semiconductor house's own packaging division will have to start driving integration technology to survive.
NEC, for one, intends to try, hoping to capitalize on strengths in both electronic systems and chip design. Though its LSI development is mostly focused on system chips, "we also intend to take up aggressive development of SiP," say sources in NEC's Electron Device Solutions Technology Group.