Spin-on stacked films for low-keff dielectrics
07/01/2001
Michael E. Thomas, Honeywell Electronic Materials, Sunnyvale, California
overview
The 2000 International Technology Roadmap for Semiconductors has identified the production requirements of low-k dielectrics extending over three device generations. The question facing the industry is "What is the best method for depositing low-k films: spin-on or CVD?" This article proposes a pathway that will address the capability, extendibility, and manufacturability options afforded by the use of spin-on low-k dielectrics in meeting the ITRS requirements and 300mm production needs.
With recent integration demonstrations of low-k materials into device structures [1, 2], spin-on low-k dielectrics are poised for integration with Cu interconnect technology in production. At present, manufacturers are evaluating the cost of tooling their 300mm factories with interconnect formation processes that need to span three device generations, the 100-50nm technology nodes delineated in the 2000 International Technology Roadmap for Semiconductors (ITRS). The issues that need to be addressed involve five key areas (Fig. 1):
- Do materials that meet ITRS technology [3] needs exist and can they be readily synthesized?
- Have the materials been integrated into existing interconnect flows?
- Have tool/material systems required for manufacturability been characterized?
- Are the material delivery systems clean and suitable for large-scale production?
- Is there a global supply chain to support new materials and tool sets?
CVD versions of high-density plasma (HDP) fluorosilicate glass (FSG) materials with k ≈3.6 are being used in production to give some improvement over HDP SiO2, k ≈4.0. However, this material does not meet the true low-k needs of the industry for the future. In addition, HDP FSGs have a fluorine limit due to corrosion concerns that prohibit appreciable reduction of keff much below this value.
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Figure 1. The key components required of a low-k dielectric technology for manufacturing.
The Roadmap points out that there is currently no known low-k solution to meet production needs at the 100nm technology node, requiring a keff = 1.6-2.2. However, spin-on dielectrics may offer low-k advantages that to date have not been delivered by chemical vapor deposition (CVD) techniques.
Spin-on low-k dielectrics are molecularly designed with well-controlled properties, can be deposited under benign deposition conditions of spin processing, and are available with k values of ~2.5-2.6 for inorganic and organic solid polymeric materials. "Solid" polymeric material refers to materials having no physical porosity, that is, nonporous dielectrics. Many believe extensions to keff ≈2.0 are feasible for existing spin-on material systems by adding reasonable (10-40%) amounts of porosity (Fig. 2).
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Figure 2. The low-k advantage afforded by spin-on dielectrics.
Al-based technologies are expected to dominate interconnect manufacturing until 2004. At this time, Cu-based interconnects are expected to have attained appreciable industry implementation. By using spin-on low-k dielectrics with Al, higher performance can be achieved without adding extensive expense to existing factories. Because porosity can be controllably incorporated with inorganic and organic spin-on dielectrics, effective k values can be improved significantly. Furthermore, spin-on low-k materials can be combined to achieve keffs at or below ~2.8. However, for CVD dielectrics, there are no low-k alternatives for Al-based technology with keff values below 3.0.
 Figure 3. Three schemes are presently being evaluated to provide an all spin-on solution for future interconnect processing. |
For Cu dual damascene (DD), spin-on low-k stacks have particular advantages — they can be used as etch stops and hard mask layers. In contrast, CVD adversely impacts the stacks, since CVD cap dielectrics are not low-k. In particular, high-k SiNx and SiCx cap and etch stop dielectrics provide poor transfer layers because they can increase the keff of the dielectric stacks. Low-k spin-on material cap and barrier dielectrics are presently under development and evaluation to address the entire manufacturing problem. In this discussion, only the trench, via, and cap ILD layers are addressed in the context of low-keff. Admittedly, Cu barrier dielectric can have an impact on the overall low-keff. However, we are pursuing spin-on Cu barrier options with k values <3.0 that will ensure the keff argument in this discussion is preserved. Finally, in terms of manufacturability, spin-on dielectrics enable the introduction of intermediate stop layers in the dielectric stack that delineate the trench and via depths without penalizing the low-keff.
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The evolution toward spin-on
For the past decade, polymer chemists have been designing and building inorganic- and organic-based low-k materials to meet anticipated industry needs. The challenge has been to develop readily synthesized organic and inorganic polymers having the acceptable physical strength and thermal stability required for IC manufacturing. The result has been the generation of a wide variety of new low-k polymeric materials synthesized by novel molecular design.
Today, solid organic and inorganic materials have been designed and manufactured with dielectric constants having k values of ~2.5-2.6 and impressive thermal stability, exceeding 450°C for extended process times (see table). The incorporation of porosity into these materials along with their low starting k values facilitates a lower keff without the need to introduce excessively large pore volumes in the material. This situation provides a much lower potential keff for future device generations. Intensive R&D effort to create simpler porosity-forming processes in these materials has been undertaken at Honeywell Electronic Materials (HEM). Families of both solid and porous materials, based on highly aromatic polymer systems and siloxane materials, have been developed and integrated into devices and device test structures [1, 4, 5]. HEM is proposing a low-keff pathway for the future, employing the use of multiple spin-on polymers to generate Cu DD interconnect (Fig. 3). By using combinations of these inorganic/organic systems, a number of advantages can be realized. All films, for example, can be completely deposited in a relatively inexpensive tool set using spin processing. Low-k dielectrics can be stacked, providing the main dielectric, etch stop, and barrier layers. This approach allows all layers to be deposited in a sequential manner using one pass through a properly configured spin tool. The throughput of the process can also be very high (~60-100 wafers/hr) with proper hot plate cure staging during the spin-on deposition process. Further, the high etch selectivity between the organic and inorganic layers in the stacked dielectric allows use of very thin resists, which provides greater lithography depth of focus latitude and better control over deep submicron feature delineation. For the structures shown in Fig. 3, the top inorganic spin-on layer acts as a lithographic hard mask.
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Figure 4. SEM cross section of a dual damascene process employing organic low-k dielectric (FLARE, k = 2.85) and CVD etch stop layers. Courtesy of Sony Corp.
The combination of solid inorganic/organic stacked dielectrics will easily achieve a keff well below 3.0. For instance, by using a combination of a siloxane-based low-k dielectric, such as HOSP with k ≈2.6, and an organic low-k material, such as FLARE with k ≈2.85, it is possible to provide a keff ≈2.7. The encouraging part of this analysis is that the effective ks of these stacks can be achieved using porosity-free materials. By introducing reasonable amounts of porosity into spin-on organic or inorganic materials having substantially low starting dielectric constants, it should be possible to provide the low-k values required for future device generations. This is the key advantage of employing spin-on stacked dielectrics.
Multistacked dielectric structures
The feasibility of multistacked spin-on dielectric structures is being demonstrated. Figure 4 shows a recent "state-of-the art" stack technology that employs both spin-on and CVD alternating layers [1]. The device structure uses FLARE organic dielectrics sandwiched with CVD oxide layers and Cu. This interconnect dielectric provides a substantial advantage over conventional FSGs and HDP oxides in device performance due to the reduction in the interconnect capacitance (~20-25%) using the spin-on materials. Other demonstrations of this approach have been reported recently that follow this technology pathway [2].
 Figure 5. A dual damascene structure uses HOSP as the interlevel dielectric with Cu. Courtesy of Sematech |
Figure 5 shows a scanning electron microscope (SEM) cross section of HOSP integrated into a DD interconnect structure with Cu [6]. This advanced nonporous inorganic material has one of the lowest dielectric constants attainable for this class of materials (k = 2.6). HOSP has also been integrated into subtractive Al process flows [6, 7]. The subtractive Al system does not require that a CVD liner be placed around the Al metallization prior to the application of the HOSP spin-on film. Borderless vias having sizes down to ~0.22µm have shown properties equal to HDP SiO2, while providing higher throughput and performance due to the substantially lower dielectric constant between metal lines. This material family can be extended to lower-k values by the addition of porosity.
Nanoglass E, a chemical analog of HOSP, is a porous material that is simple to process, can be directly polished using CMP, is extremely hard, and has a dielectric constant of k = 2.2. Nanoglass E does not require any special spin track modifications (i.e., an aging chamber) to generate porosity like other versions of this material and has small pore sizes, ~2nm.
Stacked dielectric structures as shown in Fig. 2 have now been created at the HEM Star Center. A SEM of these structures in Fig. 6 demonstrates the high etch selectivity between inorganic and organic dielectrics. Figure 7 demonstrates the simultaneous etching of the organic dielectric as well as the ashing of the photoresist. The inherent high degree of selectivity between inorganic and organic dielectrics can eliminate the variability associated with timed etch processes.
Manufacturability
By locking down the chemical characteristics of the materials in the stack in terms of application and etching, little if any change will be required in the tool set or process flow. This is possible because the only property that changes in the stack is the degree of porosity in the materials. And since the chemical nature of these materials will not change through the addition of porosity, the production process and tool set required for multiple generations of technology will remain essentially unaffected. This approach should dramatically improve the cost of ownership (CoO) of future spin-on dielectric interconnect processes, with only the cost of adding porosity needed to lower k values further.
Studies performed on FSI and TEL spin tracks demonstrate that production control is already possible with mature coating systems. A 64,000-point thickness map (Fig. 8) of a FLARE spin-on dielectric applied with an FSI 300mm coater indicates a thickness of 1053nm and uniformity of 50Å. Using routine techniques to tune the track, 6s film uniformity was held to 3.6nm over the whole wafer with a total variation of ~5nm. This standard deviation for the film divided by the mean thickness yielded a nonuniformity <0.03%. Similar uniformity for FLARE films has been demonstrated on a 300mm TEL coater (Fig. 9). The reproducibility of the film thickness across the 300mm dia. of the wafer was excellent. A series of wafers were spun sequentially to generate a nominal 500nm film. The thickness reproducibility was again significant with a mean value of 494.1nm and nonuniformity (1s/mean) of 0.6%. The total 3s spread for all wafers was 9nm.
Our experience has shown there are many tools in the field capable of delivering high-quality spin-on dielectric films. Spin-on dielectrics and the spin tracks used to deliver them are mature and ready for 300mm production. It is also important to point out that the capital cost of spin-track tooling is substantially lower than comparable CVD equipment at equivalent wafer throughputs. Since spin tracks do not require the complexity of vacuum and custom-designed process modules, tool extendibility becomes quite attractive.
Our CoO analysis, based on industry standard models, indicates that spin-on technologies are considerably more attractive than CVD processes, especially as manufacturing volumes increase. The throughput of a single spin track along with its lower capital cost provides a distinct cost and floor space advantage over CVD systems. Disparity in this area becomes more pronounced as the required interlevel dielectric film thicknesses increase in the upper levels of metallization.
New developments in spin-on dielectric delivery systems have also made great strides in the past few years. Large volume delivery systems, ~60 liters, are being introduced into production, allowing ease of use, reduced maintenance, and highly defect-free, spin-on film generation. One example, a delivery system from Microbar, enables large-volume capacity, temperature control, metered dispense, and filtration. This tool is Web-enabled and allows external system monitoring and control. The implementation of such an approach improves the handling and maintainability of spin-on materials, leading to less frequent bottle changes and better defect management.
Conclusion
Spin-on dielectric technology is positioned for introduction into 300mm manufacturing. We have proposed a simple strategy that will allow the industry to implement low-keff interconnect dielectric solutions, which will provide extendibility of existing tool sets for at least three technology generations. Manufacturers are currently evaluating the use of these spin-on organic and inorganic materials at the 130nm technology node and below for production of devices by mid to late 2001. The ability to use these novel, stacked structures and to achieve a much lower keff should provide a powerful and straightforward technology pathway to meet the ever-accelerating time lines of semiconductor manufacturers.
Acknowledgments
Stacked Dielectrics, HOSP, Nanoglass, Star Center, GX-3, and GX-3P are trademarks of Honeywell Electronic Materials. FLARE is a registered trademark of Honeywell Electronic Materials.
References
- T. Hasegawa et al., "Copper Dual Damascene Interconnects with Low-k (keff <3.0) Using FLARE and an Organosilicate Hard Mask," Technical Digest of the International Electron Device Meeting (IEDM), pp. 623-626, 1999.
- R.D. Goldblatt et al., " A High Performance 0.13µm Copper BEOL Technology with Low-k Dielectric," Proc. of the International Interconnect Technology Conference, p. 261, June 5-7, 2000.
- Semiconductor Industry Association, International Roadmap for Semiconductors, 2000 Ed.
- K. Tokumaga et al., " A Reliable Interconnection Technology Using Organic Low-k Dielectrics for 0.18µm CMOS Circuit," Proc. of the 1999 International Conf. on Solid State Devices and Materials (SSDM '99), pp. 498-499, 1999.
- J.C. Sum et al., "Process Integration of a Direct-on-Metal, Non-Etchback, k = 2.5 Polymer for the 0.18µm CMOS Technology Node, Proc. of the 1999 International Interconnect Technology Conference, pp. 184-186, May 24-27, 1999.
- Sematech, private communication, 1999. See Fig. 5.
- T. Yoshie, S.C. Chen, J. Kanamori, "O2 Plasma Treatment of Low-k Organic Silsesquioxane for Novel Intermetal Dielectric Application," Proc. Advanced Metallization Conference, Orlando, FL, p. 467, Sept. 28-30, 1999.
Michael E. Thomas received his BSE in chemical engineering and metallurgical engineering in 1973, and his MSE in 1975, from the University of Michigan, Ann Arbor; he received his PhD in materials science and engineering in 1979 from Stanford University. He was a co-chairman of the 1994 and 1997 SIA National Technology Roadmap for Semiconductors Committee for Interconnect Technology and is named as an inventor on more than 35 patents. He is presently CTO and manages the Star Center, a materials integration facility, at Honeywell Electronic Materials, Wafer Fabrication Materials, 1349 Moffett Park Drive, Sunnyvale, CA 94089; ph 408/962-2000, fax 408/980-1430.