Cluster tool sputtering for compound semiconductors
07/01/2001
Andy Bavin, Trikon Technologies Inc., Newport, UK
overview
With increasing demand for high-performance optical and communications devices, the drive for mass fabrication of III-V components is forcing many manufacturers to examine the limits of their processing technology. The move from 100 to 150mm-dia. GaAs substrates has significantly increased the CoO of traditional metallization equipment. This article examines the various metallization processes used in the fabrication of GaAs devices and discusses the impact of sputtering in reducing CoO.
Recent developments in sputtering technology have enabled physical vapor deposition (PVD) to become a viable, cost-effective alternative to evaporation for the metallization of compound semiconductor devices. The lessons learned from the silicon industry show that changing from batch evaporation to cluster tool sputtering can lead to major improvements in productivity. This is relevant for gallium arsenide (GaAs) device manufacturers as they ramp from small- to large-scale production.
To understand the requirements of a particular deposition method, it is first important to examine the different types of metallization processes used to fabricate modern GaAs devices. Many of these processes parallel Si metallization schemes, but there are some fundamental differences that must be taken into account.
Metallization
GaAs metallization schemes employ a wider variety of materials than their Si counterparts. The table displays a list of the most common materials used and their primary roles within particular deposition applications. Essentially contacted in the same way as Si devices using either ohmic or Schottky contacts between the metal and the semiconductor, III-V materials, in general, require multilevel metallization.
GaAs ohmic contacts are formed by depositing several materials with incremental work functions, one on top of another, until the combined, contact metal work function is equal to that of the semiconductor. Since an n-type GaAs cannot be grown epitaxially with a high enough dopant level to form a direct ohmic contact, a Ni/Ge/Au stack is commonly deposited.
Following metallization, a short furnace anneal is performed to diffuse the Ni and Ge into the GaAs, raising the n-type dopant level and forming an ohmic contact.
 Figure 2. Cross section through a GaAs power device showing a typical backside via structure. |
Typically, no extra doping is needed for p-type contacts in current GaAs devices; usually, a simple Ti/Pt/Au stack is deposited. Titanium aids metal adhesion and platinum prevents the gold from reacting with the titanium during subsequent anneals. Although expensive, the top contact layer is commonly Au as it has a high electrical conductivity, high resistance to oxidation, and minimal reactions with other materials. Al readily forms eutectics with GaAs, such as AlGaAs, and therefore cannot be used.
Schottky contacts can be fabricated with single or multiple metal depositions. The doping level of the semiconductor and the required Schottky barrier height dictate the precise choice of metals. Often, tungsten and tungsten silicon are used.
 Figure 3. Cross section through a simple thin-film capacitor and resistor. |
GaAs metallization layers are rarely patterned by dry etch processes, as in Si applications, because Au has nonvolatile by-products and must be sputter etched. Therefore, the contact metal is patterned using a resist "lift-off" technique. A film of photoresist is spun onto the wafer, then exposed and developed to form a mask for the metal deposition. The exposed windows in the resist are patterned so that, in cross section, they have a re-entrant or undercut profile. This ensures that the deposited metal does not form a continuous film over the window sidewalls, enabling the resist to be chemically stripped from the wafer, leaving only the patterned metal behind (Fig. 1).
Interconnect metallization
Although the materials used in GaAs processes differ from those used in Si, interconnect metallization schemes are similar, often consisting of adhesion, barrier, and conducting layers. TiW, TiWN, or a layer of each may be used for adhesion and barrier, although a consecutive deposition of Ti and Pt is often favored due to lower resistivity. The conducting layer is most commonly composed of two independent Au depositions. A thin seed layer is deposited using a PVD technique followed by an electrochemical deposition (ECD) technique used to selectively and economically deposit the bulk of the conducting layer. Following blanket seed deposition, the bulk conductor is deposited onto a resist mask. After lift-off patterning of the thick (>1µm) Au, however, the deposited seed layer remains on the wafer and must be sputter etched from the surface to prevent the interconnects from short-circuiting.
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Air-bridges between multiple interconnect levels are highly reproducible and have extremely low stray capacitances. Constructed using resist removal, air-bridges comprise a supporting resist layer that defines the designated area and height of interconnects residing above an underlying metal track. A second resist layer is used as a lift-off mask to define the upper interconnect itself. Following metal deposition, both layers of resist are removed, leaving the newly deposited upper interconnect as a bridge over the wiring below.
Backside via metallization
When manufacturing GaAs power devices, there is a need to fabricate low-impedance contacts to ground, requiring connection to the emitter pad through the substrate material. When frontside processing is completed, the front surface is sealed in a polyimide film and mounted facedown to a carrier with wax. The wafer is then ground to a thickness of approximately 200µm and the backside is patterned and etched to form the contacts (Fig. 2). A thick (>2µm) metal conductor connects the backside of the wafer to a contact pad, thus providing electrical contact and acting as a heat sink to compensate for GaAs's poor thermal conductivity (one third that of Si).
Metallization of the backside via is implemented using a process similar to frontside metal interconnects. A thin film of Ti or TiW is deposited as a PVD adhesion promoter prior to a Au seed layer and bulk conductor. The adhesion and seed films may be deposited directly onto the back of the wafer. At the thicker ECD layer, however, the edges of the chip must be masked or etched to prevent delaminating the conductor during dicing of the wafer. No other patterning is generally required for the backside via metallization process.
Integrated passive components
In microwave monolithic integrated circuit (MMIC) devices, thin-film resistors and capacitors can be deposited onto the wafer using the lift-off technique, thereby integrating components into upper-level interconnects. Of the many capacitor designs, metal-insulator-metal (MIM) is most commonly used by MMIC manufacturers. Following the base electrode deposition using PVD, a thin film of Si3N4 or Ta2O5 is deposited onto an area defined by a resist mask. The upper electrode is then deposited atop the insulating material, followed by lift-off. Thin-film resistors are fabricated in a similar manner, but consisting of NiCr or TaN. For both capacitors and resistors (Fig. 3), the characteristics of the material, resist area, and film thickness define performance.
Sputter cluster tools
Larger wafers and higher volumes are generating a demand for mass production equipment like that used in the Si industry, spurring the move from batch evaporation tools to cluster sputter tools (Fig. 4). Cluster tools have demonstrated significant advantages in 150mm wafer productivity over evaporation, largely attributed to their cassette-to-cassette operation and fully automatic wafer handling. These factors reduce operator time required to manually load and unload the tool, thus minimizing the operating costs and reducing wafer damage and breakage. Dual cassettes also mean that wafers can be processed continually through the system with no load and vent overhead. Therefore, the throughput of sputter cluster tools is limited by the process time and speed of the robot wafer handler rather than the number of wafers that can be processed in the reactor. For 150mm GaAs wafers, cluster tools can match and even exceed the throughput of batch evaporation tools.
 Figure 4. Trikon's Sigma fxP sputter cluster tool. |
Process control is enhanced by using single-wafer cluster tools, including tuning of individual film parameters such as stress and resistivity. There is also a growing body of evidence to show that high-density sputtered films produce significantly lower yield losses than their evaporated equivalents.
Unlike batch evaporation systems where several materials are often deposited in the same chamber, individual, ultra-high vacuum deposition modules ensure near-zero cross-contamination even when performing reactive depositions in a N2 or O2 ambient. Furthermore, material reclaim from the chamber shielding is often more efficient, ensuring a lower cost of ownership (CoO) for the deposition of precious metals.
GaAs applications
In spite of apparent benefits, there has been reluctance within the III-V community to make the move from evaporation to sputtering. Common concerns include difficulty of lift-off processing, inadequate handling of delicate GaAs substrates, and cost issues when applied to GaAs processes.
 Figure 5. An alternative to physical clamping, the cold electrostatic chuck provides low-temperature depositions onto GaAs substrates. |
Unlike Si schemes that are often processed at moderately high temperatures, GaAs metallization is generally performed cold. Fundamentally, this is because arsenic (As) diffuses from GaAs at temperatures >400°C. However, there are further temperature considerations to take into account. Lift-off applications use a photoresist mask that will reticulate at temperatures above 80-100°C, causing them to bake hard to the surface of the wafer and preventing removal. Further, backside processes are performed on wafers mounted to carriers with an adhesive wax that is designed to melt and de-bond the wafer from the carrier at temperatures >100°C.
Unlike evaporation, plasma heating and the heat of condensation make sputtering an inherently warm process. Therefore, the wafer must be cooled to prevent significant heating during deposition. The low pressures used during sputtering make clamping a necessity to ensure good thermal conductivity between the wafer and the cooled platen. However, physical wafer clamps can damage brittle GaAs wafers, increase particle levels, and must be changed frequently due to the buildup of deposited material, thus reducing module uptime.
Trikon's electrostatic chucks (ESCs) were developed as an alternative to physical clamping. The ESCs use a bipolar electrode to electrostatically clamp the GaAs wafer (Fig. 5). A thick-ceramic, high-clamping voltage design introduces argon gas between the wafer and the chuck to improve thermal contact and efficient wafer cooling. The high clamping voltage allows wafers to be clamped through insulating carrier materials without metallizing the carrier. This eliminates the need for a carrier coating and cleaning during backside metallization processes and enables easy wafer/carrier separation. Device damage is prevented by the capacitive effect of the thick ceramic. Reversing the positive and negative electrodes after every clamping cycle prevents charge buildup on the ceramic and increases the lifetime of the ESC.
Directional deposition
The need for directional deposition in Si processing is driven by the need for effective liner and barrier materials in small contact and via features. In GaAs processing, seed layers must form a continuous film into backside vias, requiring good sidewall coverage. Also, lift-off processing relies, in part, on the directionality of deposition to successfully remove resist following metallization.
Several techniques can be used to increase the normal component of a sputter deposition. For example, physical collimation uses a metal grid placed between the target and the wafer, but has long been thought of as an inefficient and dirty process. The buildup of material on the collimating grid reduces the effective deposition rate, generates particles above the wafer, and reduces the module uptime due to the need for regular chamber cleaning.
One method originally developed for Ti/TiN barrier deposition reduces the amount of low-angle material from reaching the wafer by increasing the target-to-substrate spacing. Called long-throw deposition, the reduced efficiency of precious target materials such as Au and Pt is compensated for by the use of Al flame-spayed shielding. When removed from the chamber at the end of target life, the Al can be chemically stripped from the shield with a simple potassium hydroxide (KoH) dip, causing the deposited material to flake off. The chemical bath is then filtered to recover these flakes. Because this process does not dissolve the deposited material, and the chemicals used are relatively inexpensive, up to 80% of the deposited material costs can be reclaimed.
Wafer handling
Extensive reliability and production data is essential for deposition equipment in the III-V's market. The cost of a 150mm GaAs wafer, following epitaxial growth of the device structure, is roughly 60 times that of an equivalent Si wafer. Poor handling can therefore be a very costly problem.
Because frontside and backside processes are very similar, it is economically beneficial if both applications can be performed in the same tool. This means that the system must be able to handle both GaAs wafers and thinned GaAs wafers on quartz or sapphire carriers, however, leading toolmakers to consider two major implications. First, wafers and carriers are rarely the same size. Carriers are generally 6-9mm larger in diameter to prevent the mounting wax from spreading to the edge of the carrier and contaminating process equipment. Second, wafers and carriers have different masses and coefficients of friction. Robots must be able to quickly move both substrates from module to module without mishandling them.
Since many sputter tools are dual cassette systems, the problem of two wafer sizes is easily resolved by processing frontside wafers from one cassette and backside wafers from the other. Reliable substrate handling can be controlled by adjusting the acceleration profiles of the robot's motion.
Process control
Evaporated alloys are often codeposited from two separate materials in the same chamber, for example, Ni and Cr for resistors. Because of the difference in the materials' vapor pressures, it is often difficult to obtain a repeatable film stoichiometry using this method. Sputtering, however, can provide repeatable control of stoichiometry by depositing from a pre-alloyed target (e.g., NiCr). A similar level of control is also possible when performing a reactive deposition, such as Si3N4 for capacitors or TiWN for barrier layers. Stoichiometry control ensures that critical components are manufactured with repeatable film resistivity/capacitance and stress, thereby increasing product yield.
Conclusion
The increase in GaAs production is driving the change to 150mm-dia. wafers and generating a desire within the industry for high-throughput, high-yield deposition equipment. Sputter cluster tools have been shown to provide similar benefits in productivity to those used in the Si industry. Benefits specific to GaAs metallization processes make sputtering an attractive process for contact, interconnect, backside, and component deposition in high-volume manufacturing facilities. By adapting production-proven Si sputtering equipment to the particular needs of the GaAs industry, sputter cluster tools are becoming a viable and cost-effective alternative to traditional evaporated metallization schemes.
Acknowledgments
Sigma is a copyright and fxP is a trademark of Trikon Technologies Inc.
Andy Bavin received his degree in physics from Bath University. He joined Trikon Technologies in 1996, and is currently PVD marketing engineer. His responsibilities include the development and implementation of marketing and sales support programs and promotion of Trikon's PVD equipment. Trikon Technologies Inc., Ringland Way, Newport, South Wales NP18 2TA, UK; ph 44/1633-414-000, fax 44/1633-414-141, www.trikon.com.