New metrology challenges met by elastic probe technology
07/01/2001
William H. Howland, Robert J. Hillard, Solid State Measurements Inc., Pittsburgh, Pennsylvania
overview
A new nondestructive elastic probe technology enables semiconductor manufacturers to conduct advanced electrical testing on product wafers at production speeds. The cost savings can be enormous, and the accuracy and flexibility of the technology facilitate continued miniaturization.
The performance requirements for advanced gate metrology are changing rapidly and dramatically [1]. Over the next five years, semiconductor manufacturers will deploy thin oxides, nitrided oxides, and nanometer scale high-k dielectric gate insulators. Many of the challenges in front-end processing involve the precision of the measurements of these advanced gate materials. Breakthroughs in metrology are essential to the introduction of these new materials and processes.
Gate dielectric measurement challenges
Currently, the equivalent oxide thickness (EOT) is 1.9-2.5nm for logic devices and 3.0nm for DRAM devices. By 2005, the EOT for logic and DRAMs will decrease to 0.45nm and 1.0-1.5nm, respectively [1]. Measuring EOT in the 0.45- 2.5nm range with the desired precision of ±4% will challenge available testing technology. Correlating optical or physical measurements with the electrical parameters that control device operation is an additional challenge. Making such measurements on product wafers at production speeds further complicates the issue. Metrology equipment designers are attempting to meet this challenge with new technologies, because currently available products are unable to satisfy these exacting requirements.
One difficulty that metrology faces is the discrepancy among the physical oxide thickness (PTox), the optical oxide thickness (OTox), and the electrical oxide thickness (ETox). The PTox is the distance between metallurgical junctions. The OTox is the thickness that an ellipsometer "sees." The ETox (or the thickness that the device "sees") is the distance between the edge of the free carrier distribution in the gate and the edge of the free carrier distribution in the channel. As PTox shrinks, the differences between ETox, OTox, and PTox become more significant. The causes of these discrepancies include:
- polysilicon depletion effects,
- quantum mechanical effects,
- the absence of abrupt metallurgical junctions at the polysilicon/silicon dioxide and silicon dioxide/silicon interfaces, and
- sensitivity to varying nitrogen levels.
Polysilicon depletion effects result from the space-charge region that forms in the polysilicon gate during gate biasing. This space-charge region shifts the carrier distribution away from the polysilicon/silicon dioxide interface and increases the ETox. The OTox and PTox do not change, however.
Quantum mechanical effects are the result of a quantum well that forms at the silicon dioxide/silicon interface during gate biasing. The carrier distribution shifts away from the interface, increasing the ETox. Again, ETox, which is important to device operation and electrical measurements, changes, but OTox and PTox do not.
Because the metallurgical junctions at the interfaces typically are not abrupt, the exact location of a junction, and hence the measurement of layer thickness, depends on how the measurement technique defines the junction location. Finally, one recent series of measurements has shown that varying levels of nitrogen in silicon dioxide yield different ETox as compared to OTox.
 Figure 1. Elastic probe high frequency capacitance-voltage curve before and after sulfuric peroxide removal of 15Å surface organic layer. |
Most available dielectric thickness metrology techniques, such as x-ray and neutron reflectivity, high-resolution TEM, angle-resolving XPS, SIMS, and spectroscopic ellipsometry, do not take into account PTox/ETox and OTox/ETox discrepancies. These techniques measure the PTox or the OTox while making assumptions about the location of naturally graded interfaces or interfaces with nearby material composition and stoichiometry changes. Differences also exist among various ways to measure PTox, as well as between the PTox and OTox measurements. For example, SIMS does not intrinsically agree with ellipsometry in defining the position of the silicon dioxide/silicon interface. Additionally, for thin oxides below 10nm, the OTox and the index of refraction cannot be deconvolved. Consequently, the dispersion of pure oxide is used to model the dielectric film. For nitrided oxides, this will lead to a higher OTox than PTox.
What really matters to device producers is what the semiconductor device experiences in operation and not what a measurement technique "sees." An electrical measurement technique involving the same interface issues as the operating device should yield the dielectric thickness measurement that is the best predictor of final product performance. ETox measurements should include these interface phenomena.
Device designers face not only these interface difficulties, but also the end of the useful life of silicon dioxide as a gate dielectric. The cause is direct quantum mechanical tunneling. Even if the oxide is free of defects, impurities, or variations in stoichiometry, it will still leak substantially at thicknesses below 3nm. This tunneling current can change by several orders of magnitude for just a few angstroms change in thickness. To complicate matters further, the oxide quality typically is imperfect, leading to other current transport mechanisms that can increase the leakage current and accelerate gate oxide failure. Gate engineers are trying to reduce this leakage by improving the processes required to produce thin gate oxides. For current and future gate oxides, monitoring gate oxide leakage current will be necessary.
Eventually, high-k dielectrics will replace or augment silicon dioxide. These materials will allow designers to achieve the desired thin EOT structures while maintaining a thicker, more robust PTox. Gate engineers are currently working to understand the electrical properties of these high-k structures. Once incorporated into gates, the structures will have to be monitored for leakage current and interface quality.
Metrology that is merely sensitive to electrical properties and that correlates with device characteristics is not good enough. A measurement technique used for process development and gate process control must be accurate and repeatable, as well as sensitive. In addition, the technique must work on product wafers at production speeds in order to be considered for in-line monitoring.
Device manufacturers using 300mm wafers increasingly wish to eliminate monitor wafers. Monitor wafers are costly, and they consume valuable factory capacity. Monitor wafers also require special routing, typically with manual intervention, but 300mm factories are increasingly automated. The diminished role for human operators in such factories means that the periodic manual insertion and removal of monitor wafers is becoming more difficult.
All existing process monitoring tools that are sensitive to gate dielectric thickness and gate quality operate on monitor wafers. Monitor wafers are necessary because these tools have spot sizes orders of magnitude larger than those required to measure in scribe lines or test structures, or the tools may contaminate the dielectric surface or require time-consuming gate formation processing.
The elastic probe approach
Metrology engineers have developed a new probe, with a diameter of about 30µm, from material compatible with semiconductor processing [2]. The probe's small diameter allows for proper probe placement within product wafer scribe lines and on product wafer test structures. The new probe elastically deforms to the dielectric surface, forming a small diameter gate. This intimate metal/dielectric contact eliminates air gaps at the probe-dielectric interface that could lead to erroneous measurements.
The small diameter elastic probe eliminates measurement circuit parasitics that have plagued conventional C-V measurements using polysilicon test structures. The metal oxide semiconductor (MOS) test structure traditionally used for these measurements is modeled as one component in the equivalent measurement circuit. This test circuit includes parasitic elements resulting from cabling, meters, and other components. The elastic probe technology creates a contact area less than 1% of that found with conventional C-V structures. As the gate or contact becomes as small as possible, the test structure becomes the "bottleneck" for displacement current and therefore becomes the dominant equivalent circuit element during measurement. The elastic probe also makes high frequency C-V measurements, which provides an advantage over DC measurements because high frequency measurements increase the displacement current, permitting more accurate measurement of capacitance and thereby of the dielectric thickness.
Organic contaminants and moisture can adsorb to a thickness of 0.1nm over the first hour after a gate dielectric has been grown [3-5]. An organic layer of 1.0-1.5nm is often found on surfaces that have been exposed to a cleanroom ambient for longer periods (for six months in the example in Fig. 1). The probe's elastic deformation process displaces surface organics and moisture from the measurement site, as verified in Fig. 1. This figure shows elastic probe high frequency C-V curves before and after removal of a 1.5nm organic layer using sulfuric peroxide. Without an additional cleaning process, this surface organic layer appears as an additional thickness added onto the OTox measurement [2]. The elastic probe displaces this temporary layer and eliminates it from the ETox measurement.
A patented kinematic probe arm allows for only one degree of vertical probe motion. Spreading resistance probe products have used this technique successfully for more than 30 years. Vertical motion stops when the probe forms an elastic intimate contact with the dielectric surface. The kinematic probe design and its controlled probe descent rate prevent surface scrubbing, particle generation, or damage to the dielectric surface. This design therefore allows for accurate and repeatable probe placement.
To ensure that external vibration neither degrades the measurement performance nor causes probe scrubbing (and particle generation), vibration isolation has been designed into the tool. The vibration isolation eliminates any influences from wafer handling, atmospheric control, and, of course, human activity. Environmental control eliminates any potential probe scrubbing caused by thermal expansion and also reduces atmospheric contamination.
 Figure 2. Electrical oxide thickness as a function of various anneals. |
The probe's designers have performed extensive studies to confirm that the probe does not damage or contaminate the dielectric surface [2]. Total reflection x-ray fluorescence (TXRF) and vapor phase decomposition-TXRF (VPD-TXRF) studies verified that probe material was not being left behind on the surface. The TXRF results showed the same random distribution of elements on and off elastic probe sites. The VPD-TXRF test gathers all of the surface contamination into a small spot, and is therefore more sensitive than TXRF. The VPD-TXRF showed no trace of probe material. The particle density counts also showed a random distribution of particles. These results suggest that an environmental source of particles was present and that the probe dielectric interaction was not the source. Atomic force microscope scans also revealed no detectable damage on the surface. Finally, the designers employed the Wright etch, a selective etch that attacks damaged silicon. The Wright studies clearly showed that the probe caused no damage to the underlying silicon.
 Figure 3. Flatband voltage (oxide effective charge) as a function of various anneals. |
The elastic probe technology can measure within product wafer scribe lines and on product wafer test structures. Such measurements require very accurate and repeatable probe placement, which can be accomplished only by using state-of-the-art vision capability. The elastic probe technology uses standard, industry-proven vision capability that allows for pattern recognition after rotation to any angle. This system is also immune to changes in scale and image contrast. These variations are common during CMP processing. State-of-the-art vision systems work by recognizing geometric shapes instead of using the grid-based searching technique of older systems.
All in-line metrology systems must produce measurements at production speeds. This means, typically, that five to nine measurements/wafer must be made on 60 wafers/hour. The elastic probe technology is currently capable of making these high-speed measurements. Engineers achieved this throughput by using high-speed wafer handling systems and methodologies, as well as optimized data acquisition and analysis algorithms. These major enhancements to traditional metrology techniques have allowed true electrical characterization to evolve from a slow, off-line monitor process to an in-line quality management process that can potentially test every product wafer.
Thin oxide results
Figure 2 shows the sensitivity of ETox measurements on nine samples with varying anneal operations. Samples 2 through 4 show an expected trend of decreasing ETox with increasing nitrogen concentration. OTox will typically show the opposite trend because of an assumed index of refraction for silicon dioxide.
 Figure 4. Cumulative probability for leakage current as a function of various anneal conditions. |
The flatband voltage (Vfb) measurements of Fig. 3 show similar sensitivity to the level of nitridation. As expected, the flatband voltage becomes more negative for increasing nitrogen concentration, since increasing [N] typically results in an increase in positive charge. Note that sample 5 shows a less negative flatband voltage than the other samples, suggesting that there must be less positive charge present. Figure 2, however, shows that this sample has an oxide thickness half that of the other samples. Because the charge in the oxide varies as the ratio of the flatband voltage to the oxide thickness, sample 5 actually has more positive charge than all of the other samples.
The difference obtained by first measuring the flatband voltage while sweeping the voltage from negative to positive, and then measuring the flatband voltage by sweeping the voltage from positive to negative, is proportional to the trapped charge in the oxide. This charge differs from the effective charge measured from the flatband voltage because the effective charge usually results from fixed charges located near the silicon dioxide/silicon interface and interface state charges located at the silicon dioxide/silicon interface. The trapped charge results from the trapping and de-trapping of free carriers in oxide traps located throughout the oxide.
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Figure 5. Forward and reverse high frequency curves for Ta2O5.
One of the most important metrics for assessing the quality of thin oxides is the leakage current. In the past, it was not critical to monitor leakage current for gate dielectric process control because gate oxides were thick enough that leakage through the oxide was not an issue. With gate oxide thickness currently below the quantum mechanical direct tunneling threshold (~30nm), leakage currents can be many orders of magnitude larger than in the past. Devices with large leakage currents would require large power sources to drive them, and these large leakage currents would cause gate oxide reliability and integrity problems.
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Figure 6. Doping concentration vs. depth for a BF2 implant. PTox=18nm.
Eventually, Moore's Law will drive silicon dioxide to the end of its useful life as a gate dielectric owing to excessive leakage current, and dielectrics with dielectric constants higher than that of silicon dioxide will be needed. In the interim, the semiconductor industry is trying to extend the life of silicon dioxide by introducing impurities such as nitrogen and by growing oxides of higher quality than previously attained. Figure 4 demonstrates the sensitivity of the elastic probe as the leakage current measurements vary over many orders of magnitude as a function of the process conditions.
High-k gate dielectrics
As noted above, silicon dioxide is reaching the end of its useful life. This insulator will have to be replaced with a dielectric with a higher dielectric constant. Some of the leading candidates are tantalum pentoxide (Ta2O5), aluminum oxide (Al2O3), and zirconium oxide (ZrO2). To increase the drive current associated with a CMOS device, a device engineer might increase the gate capacitance. Such an increase has been achieved in the past by reducing the gate oxide thickness, because the gate capacitance is inversely proportional to the gate dielectric thickness. Increasing the gate capacitance can also be accomplished by increasing the dielectric constant of the gate dielectric. This method also allows for thicker gate dielectrics that serve to reduce the leakage. Figure 5 gives an example of a high frequency C-V curve obtained using the elastic probe applied to a Ta2O5 sample. Shown here are both forward and reverse curves. The hysteresis results from the trapping and de-trapping of dielectric trapped charge. The dielectric thickness or the dielectric constant can be obtained from this curve by using the highest point on the C-V curve (known as the accumulation region of the curve) and fitting the data with the proper analytical models.
The EOT can be deduced from Fig. 5 using the accumulation region of the curve. This value is not to be confused with the ETox. The EOT applies when the user extracts the dielectric thickness from the measurement while assuming the dielectric constant of silicon dioxide. In other words, for dielectric thickness measurements on high-k materials, the EOT gives the equivalent silicon dioxide thickness that would be required to yield the same capacitance as the high-k material. The ETox applies when the correct dielectric constant is used in the measurement. For silicon dioxide thickness measurements, EOT = ETox. For high-k materials, EOT = ETox*(ksilicon dioxide/kactual).
Threshold voltage adjust channel implants
The threshold voltage (VT) applied to the gate of a MOSFET is the voltage required to turn on the transistor. The threshold voltage depends on the equivalent oxide thickness, any charges in the oxide or at the oxide/silicon interface, and on the electrically active dopant profile in the channel. Because VT depends on several quantities, it is necessary to adjust and control VT through the use of a dopant implant. The dopant profile can be extracted from the high frequency C-V curve, and the integral over this profile minus the substrate concentration yields the implant dose.
Figure 6 shows an example of an elastic probe dopant profile, which agrees well with the profile measured with a mercury probe, a proven dopant profiling technique.
Conclusion
Metrology faces severe challenges over the next few years in the control of advanced gate processes. The measurement of thin silicon dioxide, thicker high-k dielectrics, and threshold adjust implants demands the superior capabilities of device-oriented electrical measurements. Elastic probe technology has demonstrated the capacity to measure thin oxides and to differentiate electrical properties not detectable through physical measurements. It also has demonstrated applicability to high-k materials. Elastic probe technology has measured threshold adjust implants successfully and has the potential for closed-loop process control on production wafers.
Acknowledgments
The authors gratefully acknowledge Bill Alexander of Solid State Measurements Inc. for his help in organizing this paper.
References
- The International Technology Roadmap for Semiconductors 1999, Semiconductor Industry Association, San Jose, CA, 1999.
- R.J. Hillard, et al., "Characterization and Metrology for ULSI Technology 2000," NIST Conference Proceedings, pp. 119-124, 2000.
- A.E. Braun, "New Materials and Limitations Challenge Thin-Film Measurement," Semiconductor International, June 1999.
- K. Saga, T. Hattori, "Identification and Removal of Trace Organic Contamination on Silicon Wafers Stored in Plastic Boxes," J. Electrochem. Soc., Vol. 143, No. 10, pp. 3279-3284, Oct. 1996.
- P.J. Smith, P.M. Lindley, "Analysis of Organic Contamination In Semiconductor Processing," Characterization and Metrology for ULSI Technology: 1998 International Conference, edited by D.G. Seiler, et al., pp. 133-139, 1998.
William H. Howland received his BS in electrical engineering and PhD in engineering science from the Pennsylvania State University. He is a senior research scientist at Solid State Measurements Inc., where he is currently program manager for their elastic probe (FastGate) projects. Howland is a member of the IEEE Electron Devices Society and the Electrochemical Society. Solid State Measurements Inc., 110 Technology Dr., Pittsburgh, PA 15275 USA; ph 412/787-0620, fax 412/787 0630.
Robert J. Hillard received his BS in electrical engineering from Point Park College and his MS in electrical engineering from the University of Pittsburgh. He has worked with the Westinghouse R&D Center, the Essex Division of United Technologies Corporation, and National Semiconductor Corporation. As senior engineer at Solid State Measurements Inc., Hillard is working on semiconductor characterization methods for advanced dielectrics. Hillard is a member of the IEEE Electron Devices Society, is the author of 36 publications, and holds two patents.