Mask gate CD variations reduced with double-step maskmaking*
07/01/2001
Il-Ho Lee, DuPont Photomasks Korea Ltd., Ichon-Si, Kyung-Do, Korea
Makoto Kozuma, LSI Logic Japan Semiconductor Inc., Ibaraki, Japan
overview
A unique double-step maskmaking process reduces pattern density variation across a reticle plate when making line patterns in an active region. As a result, it weakens the loading effect of dry etching and improves CD uniformity of these patterns. Specific work shows a drastic reduction, from 29nm to 20nm, in CD variation of line patterns for logic cells.
In IC fabrication, the polysilicon ("poly") layer is one of the critical layers that influence chip yield (Fig. 1). Gate patterns, in particular, require tight critical dimension (CD) control because the gate CD determines the gate length of a MOS transistor, hence transistor characteristics such as drive current and switching speed. On the other hand, poly interconnect CDs are less determinant of chip performance.
In lithography processing, the major causes of CD variation are swing effect, optical proximity effect, CD errors on the reticle, and stepper or scanner non-uniformities. In particular, since the mask error enhancement factor (MEEF [1]) strongly magnifies reticle CD errors when reticle patterns are printed on a wafer, reticle CD errors have become the most substantial portion of total CD variation in low-k1 lithography schemes.
To suppress reticle CD errors, vendors have been trying to decrease error factors in materials and writing systems, as well as for develop and etching processes used in reticle fabrication.
 Figure 2. Mask data for poly line directly over a) active device regions (i.e., "data 1") and b) everywhere else ("data 2"). |
Typically, however, specifications for CD variation on an advanced poly-layer reticle are much higher than the typical capability. Specifically, attempts to improve reticle CDs are hampered by a characteristic error factor in current reticle making technology: the chrome loading effect in dry etching that must be applied to make aggressive optical proximity corrections (OPC) patterns [2].
So, a key issue in improving reticle CD errors is the reduction of pattern density variations to minimize this loading effect. To solve the problem, we have developed a new double-step process that makes precise poly-line patterns over active regions that, as we have noted, are especially critical to transistor characteristics.
Double-step process
The double-step process first divides the data for a poly-layer design (the example presented follows the typical design presented in Fig. 1) into data representing the poly line directly over the active device regions and data representing the poly line everywhere else (Fig. 2). These data are used in a process flow that includes two different exposure-and-develop cycles (Table 1).
The net effect is that the original poly pattern is transferred to simple line and space patterns surrounded by a chrome field (see Fig. 2a) that is used to make the most critical portion of the mask. As a result, pattern density on the active region is independent of the distance between poly patterns and the pattern density on the non-active region. The double-step process can thus reduce pattern density variation when making line patterns on the active region, compared to conventional techniques where the original poly-layer design is patterned in one step.
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While this double step process is relatively straightforward, its development involved two key issues: First, preparation of "data 2" required adding extra patterns that cover line patterns processed in the first exposure (i.e., the "data 1" exposure). Second, we did not know whether a reticle writing system could meet our requirement for overlay accuracy.
In the double-step process, there are many joint boundaries between the first and second halves of the process. Overlay accuracy is therefore a very important factor because large overlay errors would deform poly patterns at these boundaries. To clarify these issues, we carried out a feasibility study on current reticle tools. In addition, we compared reticles made by both conventional processing and the double-step process to confirm that the latter improved CDs.
Data preparation
Figure 3 outlines our procedures used to prepare the two mask data sets. This process first extracts line and space patterns on the active region from the original polylayer design. Then, preparation of the two data sets is achieved using simple "minus" and "or" Boolean operations on a popular CAD system.
As Fig. 3 illustrates, the "minus" operation between the original active design and poly design extracts the data for the first exposure in the double-step process, which is processed as clear pattern.
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The "or" operation extracts the data for the second exposure, which is a dark pattern. Within the second half of this process, the active patterns play a role as extra patterns covering line and space patterns made at the first process. It is very important that these data procedures can be completed using the current reticle manufacturing capabilities without special modifications.
Overlay accuracy
To develop the double-step process so it serves practical advanced applications, we chose a poly-layer design used in a 180nm device, specifically for embedded logic cells and a memory cell. This was implemented on a 6 in. 4x reticle. We prepared the two data sets using an ALTA 3500 reticle writing system and processed the reticle through an ICP dry-etching system. We also applied a PSM mark that is generally used for the fabrication of phase shift masks (PSMs) to overlay the two data sets.
 Figure 4. Box-in-box CD measurement site where overlay error equals (center of 2nd box) - (center of 1st box) or (B + E/2) - (A + E + B)/2 or (B - A)/2. |
To evaluate overlay accuracy on reticles fabricated with our double-step process, we measured the distance between box-in-box marks placed on four corners of the reticle (Fig. 4). We defined overlay error as the distance between the center of the first box patterned with the first exposure (Table 1, Step 2) and the center of the second box patterned with the second exposure (Step 6). We actually used the chrome pattern widths A and B (see Fig. 4), which we measured using a KMS 310RT optical CD measurement system (Table 2).
In essence, what we were evaluating with our overlay measurements is similar to pattern deformations caused by electron-beam direct write butting errors. Typical specifications for butting error are 30-40nm (mean plus 3s) [3, 4]. Accordingly, we targeted an overlay accuracy <30nm (mean plus 3σ). We were pleased to find that our measurements of overlay error were <25nm, clearly meeting our goal.
CD uniformity
To confirm the effect of the double-step process on CD uniformity, we compared a reticle made by the double-step process with a reticle made by conventional processing. Here, we used the ALTA3500 and ICP dry etching systems for both processes. The reticle design in this experiment was similar to that in the overlay evaluation. The target reticle CD was 720nm (i.e., 180nm on a wafer). We measured CDs at the four corners of each of the six full patterns on the reticle (Fig. 5). We measured two points at each site: an isolated line and the center of line-and-space pattern.
Figure 6 shows the CD variation of each reticle made by the conventional process and the double-step process. To simplify comparison of the conventional process and double-step process, we expressed the CD variation in terms of the amount of CD error against the mean value.
 Figure 3. Boolean operations are applied between active and poly regions to achieve a) data set 1 using a "minus" operation and b) data set 2 using an "or" operation. |
We found that the double-step process drastically reduced CD variations of lines on the active region, from 29nm to 20nm. Also, the process did not show any points of large CD error as is evident on chip No. 3 in the conventional process (see Fig. 6a). Such errors strongly influence transistor performance, subsequently reducing wafer yield. In comparison, large CD errors were absent in the double-step process and all CD errors were within ±10nm. We can therefore expect yields of high performance chips from reticles via the double-step process.
 Figure 5. CD measurement sites (shaded ovals) and points (arrows). |
Furthermore, we found another improvement when we compared the differences between logic and memory CDs. A comparison of CD differences between logic and memory linewidths showed less variation with the double-step reticle fabrication process. OPC is usually applied to dense memory patterns to correct CD differences between isolated and dense lines [5]. Hence, the CD differences in the reticle fabrication must be uniform to make a precise OPC reticle. In the conventional process, however, the CD differences vary across chips. On the other hand, the double-step process decreased the variation of CD differences by ~10nm.
In general, as the reticle area to be dry etched increases, the variation of plasma condition is apt to affect CD uniformity. Therefore, we believe the reduction of etching area when making the active region at the first process is the reason behind this improvement via the double-step process.
Conclusion
We have clearly shown a double-step process using available reticle fabrication tools, for example the ALTA 3500, which exhibited sufficient overlay capability. Our technique can reduce CD variation of gate lines on the poly-layer reticle, confirming our belief that the double-step process is a concrete method to meet the reticle CD uniformity required in low-k1 lithography.
Acknowledgments
The authors thank collaborators at DuPont Photomask. We also thank the reticle-engineering group at LSI Logic Japan Semiconductor Inc., LSI Logic Corp. for the preparation of test reticle data, and Dai Nippon Screen Mfg. Co. for its support.
References
- C. A. Mack, "Mask Linearity and the Mask Error Enhancement Factor," Microlithography World, pp. 11-12, Winter 1999.
- H. Miyashita, N. Hayashi, "Current Status and Future of Maskmaking Technology," Ultra Clean Technology, Vol. 11, No. 1, pp. 15-18, 1999.
- Catalog of MEBES4500S, ETEC Systems Inc.
- Catalog of HL-800M, Hitachi Ltd.
- C-H Park, et al., "An automatic gate CD control for a full chip scale SRAM device," Proc. SPIE, Vol. 3236, pp. 350-357, 1997.
Il-Ho Lee received his BS from Kon-kuk University and MS from Seoul National University, both in physics. Lee is developing various e-beam lithography and advanced mask processes in R&D engineering at DuPont Photomasks Korea Ltd., 345-1, Sooha-Ri, Shindoon-Myon, Ichon-Si, Kyoung Gi-Do, 467-840, Korea; ph 82/336-630-1659, fax 82/336-630-1118, e-mail [email protected].
Makoto Kozuma received his bachelors and masters of engineering in material science from Tsukuba University. Kozuma is a process engineer at LSI Logic Japan.
* Based on work originally presented at the 20th Annual BACUS symposium on Photomask Technology