Adapting to the economics of SOC
06/01/2001
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Putting a whole system on a chip is a neat concept that has turned out to be tougher than it looked at first. But the trend is clear: SOC is the way of the future. With the capability of putting many millions of devices onto a single chip, it is very enticing to try to cram as much of a system as possible onto one large die. Speed and performance can be greatly enhanced, system costs can be reduced, and reliability can be improved by eliminating external wiring and assembly operations, and the form factor is ideal for portable devices. But there are many problems that have to be addressed for SOC to become mainstream.
The biggest drawback to SOCs is that they turn the basic economics of integrated circuits upside down. IC devices are traditionally designed to be multi-purpose, so that arrays of them can be mixed and matched on printed wiring boards to fit the needs of each particular system. If a device can be used in many different systems, then it can be made in huge quantities, so that costs for design and ramping to yield are spread across many millions of units. If an IC is to be application-specific (an ASIC), then there must be a large market and the design must be set. Otherwise it is too costly to design and fabricate. If changes are needed — because of performance improvements or changes in standards, for example — doing a redesign with a whole new set of masks might be cost-prohibitive.
Design and testing costs are escalating exponentially with chip complexity, and making sure that many different types of circuitry will work perfectly together creates a huge verification problem. Verification takes over half the design cycle for monster chips, and even then there may be odd combinations of operations (outlyers) that are not checked, as Intel learned to its chagrin a few years ago. Adding to the problems are the ever-higher costs of process tools and complex masks. How can these costs be recovered for runs of a few hundred wafers? Excessive power is another problem with large chips. Lower voltages help because power is proportional to the square of the voltage, but there's a limit on how low it can go. Clever design with rest and sleep modes can also cut dissipation.
Even though these problems are huge, the promise for SOCs is so great that they are being addressed, sometimes in highly imaginative ways. Japan sees the need for minifabs that can be built swiftly to make targeted chips. To make such fabs cost-effective, however, there must be changes in the design of process tools and production methods (as described in the article translated from Nikkei MicroDevices on p. 83). This pathfinding work is being done within a national project in Japan, including contributions from TEL and Toshiba. Smaller footprints will save space and flexible tools will perform multiple process steps. Processes and set-ups will be simplified and speeded up. Most plasma processing may be eliminated. Direct-write stencil ion implantation will cut the number of implant steps needed.
In Europe, there has been work on general purpose SOC chips, with a microprocessor, controller, various memories, analog and mixed signal circuits, and some programmable logic to personalize the device. These generic SOCs might be configured for many tasks, so that they could be produced in volume, as gate arrays, programmable logic devices, and similar tailorable chips have been in the past.
Foundries have been assembling libraries of reusable circuit cores to perform common functions (intellectual property, or IP) that can be assembled and combined with specialized logic for particular applications designed by each customer. Efforts are increasing to develop an IP market, which is difficult because different EDA (electronic design automation) software and design approaches make it hard to combine a number of such circuit cores into a system, and then all the devices have to be tuned to a particular set of fab processes. As standards evolve for buses and interfaces, and for combining cores designed with assorted EDA tools, reuse of existing designs will greatly increase.
Cross-licensing is enabling popular microprocessor cores to be combined with memory, an assortment of existing circuit cores, and a large field-programmable gate array (FPGA) block to personalize a somewhat generic SOC, and allow it to be restructured if future design changes are needed. Another valuable resource in future SOC designs may be reconfigurable FPGAs, which can have their architecture changed on the fly so the processor is optimally organized for each step in sequential computation.
The high costs of maskmaking, to implement reticle enhancement techniques, might be minimized by patching together proven cores with only small sectors of specially designed circuitry.
Probably all these techniques and many more will evolve to make SOCs practical and profitable. It will take time, but it will happen, resulting in profound changes to chipmaking and process technology. The cooperation required will be worth it.
Robert Haavind
Editor in Chief