Technology News
06/01/2001
Floating 3-D display seemingly out of sci-fi
Actuality Systems Inc., Reading, MA, has revealed the latest version of its "science fiction" like floating 3D display technology that could revolutionize the future of design engineering, pharmaceutical design, and medical imaging, among other potential applications. Actuality's autostereoscopic volumetric display makes 3-D images appear to float inside a special viewing dome that can be inspected 360° around the display without the use of special goggles (Fig. 1). The display seems to act as a "crystal ball" for a computer; it accepts 3-D data from standard sources and converts it into volume-filling imagery that can be seen from any angle.
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To date, this development work has created imagery comprising over 100 million volume pixels (voxels). Briefly describing its technology (Fig. 2) for Solid State Technology, Actuality's founder and CTO Gregg Favalora, explains, "A high-speed 2-D projection engine images a time series of approximately 4000-10,000 frames/sec onto a diffuse projection screen rotating at 600 rpm. Then, we use a series of three mirrors to relay the imagery to the rotating screen in a manner that ensures accurate focus regardless of the screen's angle. At or above 600 rpm, persistence of vision fuses the sequence of 2-D images into a concrete 3-D image where all focus and parallax cues are correct."
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Figure 1. Senior systems engineer Deirdre Hall and Actuality's founder and CTO Gregg Favalora look on as a 3-D display shows a 10-in. hovering image of a CT scan of a woman's skull. The photo at right shows Actuality's ability to accept data from a standard off-the-shelf molecular visualization package, displaying a DNA molecule, adding customized text in a common font, and projecting them as multicolored volume-filling 3-D imagery. This digital long-exposure photo is of Actuality's prototype 3-D display creating imagery comprised of over 100 million bitmapped voxels (198 slices, 768 x 768 pixels each) refreshed at 20 Hz.
Actuality's prototype projector is based on the Texas Instruments Digital Light Processing technology that uses a MEMS-based reflective array to create single-bit-depth frames at approximately 4 kHz. Each frame has a resolution of roughly 768 x 768 pixels, and the volume is composed of roughly 200 frames, thus achieving ~100 million voxels. The projection system creates red, green, and blue image components, yielding a 3bit (8-color) display. Proprietary spatial dithering algorithms are used to create the perception of hundreds of colors.
The special projection system incorporates a rotating triplet lens and achieves voxels at any specified x, y, and z coordinate using novel algorithms. The latter are Actuality's proprietary rasterization algorithms that convert arbitrary 3-D images into a sequence of image slices.
 Figure 2. Schematic of Actuality Systems' 3D display. |
To develop this system, Actuality teamed with programmable logic supplier Xilinx Inc., San Jose, CA, and component distributor Avnet, Phoenix, CA. The 3-D display system includes Xilinx Spartan-II FPGAs, along with a 6Gb memory bank, for graphics processing and storage. The Xilinx Spartan-II components play a crucial role in ensuring the imagery is detailed, interactive, and compatible with existing computational infrastructure. Avnet, via a dedicated business group that specifically targets start-ups, provided customer solutions including technical support, intuitive software, and hard-to-get components.
One industry expected to benefit from Actuality's 3-D display is life sciences; biochemists will be able to use Actuality's display technology to rapidly design new pharmaceuticals, a process that today requires discerning the complex shapes of molecules from two-dimensional computer screens or the use of 3-D goggles. Actuality's volumetric 3-D display is expected to allow scientists to intuitively identify new drug targets and collaboratively design applicable drugs.
As dramatic as this technology is, Actuality is still in the prototype stage. Still to come are an interactive computer interface and optimized projection optics and alignment. As Favalora says, "This is just a test, folks, and only a test. Actual performance is anticipated to be significantly higher than what is pictured here."
A tunable slurry for copper damascene CMP
Cabot Microelectronics, Aurora, IL, has developed a slurry that polishes tantalum, copper, and silicon by controlling independent slurry components. In a paper presented by Homer Chou at this year's CMP MIC conference in Santa Clara, CA, copper and TEOS removal rates were independently tuned from rates as low as 50 Å/min to as high as 1500 Å/min.
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Copper damascene processes have created the need for an extra barrier layer when polishing, due to the difficulty in polishing tantalum based materials. Focusing on the three major factors for barrier CMP processes — speed, planarization, and defectivity — CMP was performed on 8 in. blanket electroplated copper (Cu), PETEOS, tantalum (Ta) wafers. Patterned wafers contained copper lines, 0.35-50µm wide, consisting of ~1.5µm thick electroplated copper, ~0.1µm PVD copper seed, and 250Å sputtered tantalum.
A two-step Cu CMP approach was adopted, the first step using commercially available iCue 5003 slurry, with Cu to Ta selectivity of >100:1, to remove the Cu layer and stopping on the Ta barrier. Cabot's developmental slurry was subsequently used to remove the Ta barrier film and stop from the oxide substrate.
The primary function of the barrier CMP process is to quickly remove the tantalum barrier material; the second is to yield a defect-free, planar wafer. CABOT developed the slurry for a high tantalum removal rate (RR) and to independently control copper (CuRR) and SiO2 blanket removal (CuRR and OxRR, respectively) by controlling slurry components.
Shown in the table, CuRR is controlled by the interaction of two slurry components, A and B, while OxRR is controlled by a single component, C. Using this system with the tantalum blanket wafer removal rate (TaRR) fixed at ~900 Å/min, CuRR and oxide removal rate, TEOSRR, can be varied from 50-1500 Å/min.
Commonly, removal rate selectivities are either nonselective (1:1:1) where the removal rates are on the order of ~1000 Å/min or exclusive (0:1:0) in which the CuRR and OxRR are <100 Å/min and the TaRR is ~1000 Å/min. Either formulation was found to produce less than optimal wafer planarity. Therefore, a third type of selectivity, a high oxide approach (1:10:10) was used to induce reverse dishing.
Reverse dishing is a popular method by which dishing from the first step, Cu CMP phase is corrected by thinning the surrounding oxide. This approach effectively reduces overall dishing and erosion across a wide variety of features. Therefore, a higher oxide removal rate was used in optimizing the ratio of Cu:Ta:TEOSRR. When compared to nonselective and exclusive formulations, higher oxide selectivity significantly improved final planarization with a given first step slurry. Similar results are expected with a first step Cu product.
In addition to slurry modifications, Chou studied the impact of the polishing pad in achieving planarization (the best being a hard pad) and on defectivity. Defectivity can be separated into two categories: defects created by the first step slurry and those by the barrier slurry. Both slurry and pad contribute to defectivity. Ironically, while a harder pad produces the best planarization, softer pads are better in terms of defectivity. Cabot is currently investigating the nature of this tradeoff between good planarization and good defectivity.
3-D packages require less handling, space
Amkor Technology, Chandler, AZ, is expanding its development and qualification of 3-D (stacked) IC packages, including the integration of three or more die (see illustration) and supporting passive devices. The resulting packages cost less to produce, require less handling throughout manufacturing and mounting processes, require less space, and have higher reliability and better electrical performance than the combination of devices they replace.
Amkor has developed 3-D packaging options that include die stacked three or more high, stacked die of the same or different sizes, and side-by-side 3-D die stacks. 3-D assembly techniques allow mixing of interconnect technologies within the package. These include die-to-die or die-to-substrate using combinations that can include either wirebond or flip chip technologies within the same package.
 Three stacked memory die put into nearly the same area as a single chip package with full wire bonding advantages. |
3-D packaging was first introduced so mobile phones and other handheld devices could be made smaller by allowing flash and static RAM chips to be vertically stacked within a single package; Amkor has been shipping 3-D IC packages since 1999. Now, 3-D packaging is emerging as a valuable enabler in OEMs' system-in-package (SiP) designs. Stacked die packages decrease the total system cost by reducing the number of components needed as well as simplifying the application's motherboard. In addition, stacked die reduce the length of interconnects between devices, enhancing electrical performance as well as final system application performance.
Beyond these, new applications from chip sets to large memory blocks are being investigated for potential development. Current annual stacked package volumes will approach 230 million units this year, according to industry analyst TechSearch International Inc., Austin, TX. It estimates a 50% market growth to 348 million stacked packages by the end of 2002 for all applications.
For semiconductor and systems manufacturers, the cost savings of stacked IC packaging accrue in a number of ways:
- Chipmakers achieve a lower component cost. While each individually packaged IC requires its own high-density interconnect substrate (the highest-cost material in the package), a 3-D package requires only a single substrate-interposer. The cost of three-die stacked packages could be as much as 35% less than the cost of separate single die package options.
- A stacked package, or SiP, is tested as a single unit, eliminating tests for three or more individual die packages and reducing handling compared to individual packages. Subsequent testing during board assembly is also reduced because device handling generally consumes more time than an actual test. The use of known-good-die at the wafer level increases the yield of stacked packages and is an area seeing continued development to further extend the cost savings of stacked and multi-chip packaging.
- For the OEM, in addition to the 30-60% reduction in system-board area, 3-D IC packaging reduces system-board wiring density and complexity by moving this interconnection challenge inside the 3-D package. Die-to-die wiring within the 3-D package also reduces the external I/O count, allowing larger package mounting-pad pitches to be used, further reducing assembly costs and enhancing second level solder joint reliability.
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Because there are fewer components to handle, system assembly costs are also further curtailed. Additional indirect savings are realized because fewer components must be procured, qualified and inventoried. These advantages are gained with a minimal increase in mounting height for 3-D packages, which use wafer thinning and thin substrates to achieve 1.4mm for three die stacks and 1.2mm for two die stacks. Weight of stacked packages can be up to 70% less than multiple single-die packages capable of performing the same functions, an important consideration to a company supplying to consumer markets. — P.B.
The age of international cleanroom standards
There are elements of contamination control in the International Technology Roadmap for Semiconductors (ITRS) that need to be better addressed. This was the message in opening remarks to attendees of ESTECH 2001 from L. Court Skinner, director of the San Jose office of Semiconductor Research Corp. (SRC), Research Triangle Park, NC.
"Some of the difficult challenges associated with contamination control include yield models, inspection of high aspect ratio structures, trace impurity specifications, defect sourcing (the speed of collection and analysis), addressing non-visual 'no see 'em' defects, and the emerging interest in defect-free intelligent equipment," said Skinner. "Also, there are contamination control issues related to wafer environments and direct and indirect process critical materials." His challenge to attendees was for more engineers involved with contamination control to get directly involved with defining the ITRS.
Held in Phoenix, AZ, ESTECH 2001 was the 47th annual technical meeting and exposition of the Institute of Environmental Sciences and Technology (IEST). Notably, IEST is writing-guardian of the venerable, but perhaps defunct, cleanroom standard FED-STD-209 (airborne particulate cleanliness classes in cleanrooms and clean zones).
Bringing conference attendees up to date on cleanroom standards activity, Robert L. Mielke from Abbott Laboratories and ESTECH 2001 technical VP of contamination control, said, "For the past four decades, countries wrote their own national standards or used other countries' national standards. In many cases, these standards were not compatible with each other, especially when it came to cleanroom classes. Today, much of the need is being met by an ISO (Geneva, Switzerland) technical committee (ISO TC 209). Committee members are diligently working on the remainder of their standards and have an ad hoc group looking at cleanroom issues, such as clean water, gases and chemicals, and surfaces, to determine whether there is a need to write ISO standards for these subjects."
The ISO technical committee for standard 209 is made up of 19 voting member countries, subdivided into eight working groups, and 18 additional observing countries (see table).
Mielke noted that volunteer-based IEST is now involved with writing "recommended practices" and is determining which ones should become American National Standards. Specifically, IEST is converting MIL-STD-1246 (product cleanliness levels and contamination control programs) into an IEST standard and MIL-HDBK-406 (cleaning materials for precision pre-cleaning and use in cleanrooms and clean workstations) and MIL-HDBK-407 (precision cleaning methods and procedures) into IEST documents.
What about FED-STD-209? About a year ago, IEST recommended to the US General Services Administration (GSA) that FED-STD-209 not be maintained since there is now an international standard in place that sets up air cleanliness classes and provides a standard method for testing to determine if those classes are being held (i.e., ISO 14644-1:1999, Cleanrooms and associated controlled environments, Part 1, Classification of air cleanliness, and ISO 14644-2:2000 Part 2, Testing and monitoring to prove continued compliance to ISO 14644-1). "Ultimately, the fate of FED-STD-209 is in the hands of the GSA, which has sole responsibility for federal standards," Mielke says.
While the GSA has to poll pertinent government agencies prior to making a decision, this process is proceeding at a bureaucratic pace.
Mielke concluded, "International cleanroom standards are here; however, they are not all-inclusive and were not meant to be. IEST will continue to write guides, recommended practices, and standards to supplement ISO standards where additional information is warranted. Other organizations, such as ASTM, will continue to write documents to address very specific requirements. It is my opinion that the US government documents such as FED-STD-209 and MIL-STD-1246 will be withdrawn."
Sandia, Ardesta plan to commercialize MEMS and microsystems
Sandia National Laboratories, Albuquerque, NM, and the Ann Arbor, MI-based Ardesta have formed a partnership agreement to transfer microelectromechanical systems (MEMS) and microsystems technologies to start-up companies in the commercial sector. The agreement grants Ardesta nonexclusive rights and license to make and sell products using Sandia's SUMMiT technology. SUMMiT, Sandia's Ultraplanar Multilevel MEMS Technology, is an advanced five-level polysilicon surface micromachining MEMS technology that allows for increased complexity and functionality from what was previously possible.
Microsystems are devices smaller than a human hair built on silicon wafers using standard integrated circuit manufacturing. Batch-produced and inexpensive to make, they contain electrical circuitry, optical devices such as lasers, and MEMS — tiny machines that can sense their environment and take action.
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MEMS devices are typically limited to two or three levels, allowing for the creation of structures such as gears with hubs. Through surface planarization techniques, additional levels permit complex interacting mechanisms fabricated on moving platforms.
"MEMS devices, once a research novelty of arrays of spinning gears, are now finding their way into a broad range of commercial applications," says Jerome Jakubczak, manager of Sandia's MEMS Science and Technology Department. MEMS devices can be found in ink jet printer heads that dispense carefully controlled amounts of ink onto paper, automotive air bag sensors that reliably deploy a car's critical safety device, display devices that visually project information from a computer onto a large screen or wall, and video games where the player's physical motion becomes part of the game.
The agreement between Sandia and Ardesta identifies key areas of intellectual property and technology that will be further developed through future cooperative research and development agreements (CRADAs) among Sandia, Ardesta, and companies formed in the process of commercializing MEMS and microsystems. Sandia, a Department of Energy laboratory, will become a shareholder in Ardesta and in any companies started based on Labs-licensed technology and intellectual property.
"This new partnership is key to the commercialization of MEMS and microsystems devices — something we see as important to our national security mission," says David Williams, Director of Sandia's Microsystems Science, Technology, and Components Center. "Before we can use MEMS and microsystems in critical weapons systems, it must be shown they are manufacturable and reliable. The best way to demonstrate this is to commercialize them and use them in everyday products. Ardesta will help make this happen."
Ardesta's corporate headquarters will remain in Ann Arbor. Sandia will provide Ardesta with fabrication capability in its Albuquerque facility until Ardesta's fab unit is completed.
Within one year after executing a license agreement with Sandia, Ardesta will develop a design and training center in Albuquerque based on Sandia's SAMPLES (Sandia Agile MEMS Prototyping, Layout Tools, Education and Services) prototyping model, which serves as a supporting infrastructure to the SUMMiT process. The ultimate objective of SAMPLES is to help users develop innovative products by leveraging advanced design, fabrication, and characterization technologies originally developed for national laboratory applications. — R.D.
JMAR to acquire SAL; explores lithography for GaAs devices
JMAR Technologies, a provider of precision micro- and nanotechnology products, plans to acquire Vermont-based Semiconductor Advanced Lithography, Inc. (SAL), a manufacturer of 1nm x-ray lithography (XRL) stepper systems with demonstrated capabilities to sub-100nm geometries. By integrating JMAR's laser plasma x-ray sources with SAL's x-ray steppers and other supporting technologies, JMAR expects a new JMAR/SAL lithography unit to be available to manufacturers of high-speed GaAs-based devices before the end of 2002. The acquisition is subject to the completion of due diligence by both parties.
While JMAR has demonstrated some of the best laser to EUV (formerly called "soft x-rays") conversion efficiencies, the acquisition of SAL and the move to XRL proposes to address the industry's need for a cost-effective alternative to EUV, according to John Martinez, JMAR's chairman and CEO. For example, the integrated XRL system is estimated at $6 million to $10 million, depending on the configuration and level of performance, compared to $30 to $40 million, by some estimates, for EUV systems. XRL can potentially mean a four-fold cost reduction.
Over the past 20 years, extensive process development at centers in North America, Japan and Europe have demonstrated the feasibility of using XRL to produce feature sizes smaller than 100nm using synchrotrons as large, immobile, multibeam x-ray sources. In the US, with one exception, synchrotrons are located at national laboratories or educational institutions, making synchrotron based XRLs impractical. For semiconductor device manufacturing, the exposure tool must be flexible and cost-effective. Over that same period, several single-beam x-ray point-sources were in development with a goal of providing a more compact, economical alternative to synchrotrons. One approach based on "dense plasma focus" (DPF) technology is currently being evaluated.
XRL technology offers potential advantages when compared to other lithography methods, the foremost being existing proximity mask technology, which enables the use of relatively inexpensive collimators to intensify and direct the short wavelength x-rays onto mask/wafer targets. The intrinsic nature of collimated x-ray light enables lithographers to readily manufacture critical high-performance circuit features. Eliminated is the need for complex and expensive focusing optics inherent in all advanced optical lithography techniques, including DUV and EUV. XRL, however, has traditionally been faced with two seemingly insurmountable challenges: low throughput and expensive mask sets.
JMAR's PXS x-ray sources, with a patented, laser plasma, is expected to provide lower cost of ownership when compared to synchrotrons, to address both GaAs and high volume silicon device manufacturing. By increasing the intensity of the source power output, throughput can be increased. Strides in x-ray photoresists are also being make, which in turn enhances throughput. In terms of masks, XRL is currently the only technology that has demonstrated masks that meet all of the requirements for the 100nm lithography generation, noted Martinez. And the costs are comparable to that of advanced photomasks. JMAR is taking steps to find an effective, economic exposure tool for the sub-0.13µm generation.
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Hold that low-energy implant!
Some surprising results enlivened the Spring Materials Research Society meeting in San Francisco (see MRS Report on p. 42). The drive to ultra-low energy implants may be misguided, according to some surprising results from Agarwal of Axcelis for boron implants, which appear to contradict theory. Greater understanding of copper films, especially properties important for chemical-mechanical planarization, also emerged. The debate over low-k dielectrics continued — over materials, porosity needed for low-k values, and metrology, as well as between CVD and spin-on advocates.
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Tech Briefs
A researcher at Varian Semiconductor Equipment Associates, Gloucester, MA, was awarded a US patent for a technology that improves the purity of an ion beamline in ion implantation equipment. Tony Renau of Varian devised an architecture that includes a filter magnet to remove species contaminants at the source, preventing the acceleration of unwanted species into the main analysis magnet of the system. This improves the energy and species purity of the beam that reaches the wafer. The technology is incorporated in the VIISta 810 tool, a single wafer implanter for 200mm or 300mm wafers.
IBM, Armonk, NY, has announced the development of an array of transistors out of carbon nanotubes. These are tiny cylinders of carbon atoms that measure as small as 10 atoms across and are 500 times smaller than today's silicon-based transistors. According to IBM, this achievement is an important step in finding new materials and processes for improving computer chips after silicon-based chips cannot be made any smaller. Depending on their shape and size, IBM reported that the electronic properties of carbon nanotubes could be metallic or semiconducting.