Epitaxial wafer market
06/01/2001
Robert Royalty, GlobiTech Inc., Sherman, Texas
Semiconductor manufacturers primarily use polished silicon wafers (PW) and epitaxial silicon wafers (epi) as the starting material in IC fabrication. Introduced in the early 1980s, epi provides electrical characteristics not available from standard PW, while eliminating many surface/near surface defects generated during crystal growth and substrate wafer processing.
Historically produced by silicon wafer manufacturers, and to a lesser degree by IC manufacturers for internal use, epitaxial wafers require the deposition of a thin layer of single crystal material (silicon) onto the surface of a single crystal silicon wafer. The typical manufacturing flow for epi wafers is shown in Fig. 1. Common epi layers between 2-20µm are "thin" relative to the substrate thickness (610µm for 150mm, 725µm for 200mm).
Epi deposition may occur in either batch-type reactors for processing multiple wafers at one time or in single wafer reactors. Single wafer reactors provide the best layer in terms of quality (thickness and resistivity uniformity, defect levels) and are used for leading-edge 150mm products and essentially all 200mm production.
This article reviews market and technology conditions responsible for epi's transition from a niche to mainstream product, and looks at CMOS epi growth expectations.
Epitaxial products
There are four general groupings of applications for epitaxial products. CMOS semiconductors support leading-edge technologies requiring small device geometries. CMOS products represent the largest application for epi and are used by IC manufacturers for nonrepairable device technologies, including microprocessors and logic chips, as well as emerging uses within memory applications such as flash and DRAMs. Discrete semiconductors are used to manufacture components requiring precise silicon characteristics. The exotic semiconductor category consists of specialty products requiring nonsilicon material; many of these consist of compound semiconductor materials incorporating an epitaxial layer. Buried layer semiconductors employ physical separation of heavily doped regions within bipolar transistor components achieved by depositing an in-process epitaxial layer.
Figure 1. Major process steps in epitaxial wafer manufacturing showing epi deposition and the cross section of a CMOS device with an epitaxial layer. |
Epi currently represents approximately one-third of all prime 200mm wafer starts. Excluding buried layer, CMOS for logic applications accounted for 69% of all epitaxy production in 2000, followed by DRAM at 11%, and discrete at 20%. By the year 2005, CMOS logic will represent 55%, DRAM 30%, and discrete 15% [1] (Fig. 2).
Market drivers
Conditions contributing to the significant increase in CMOS epi wafer consumption have existed since the mid-90s. Responding to the semiconductor "slump" in 1997-1998, IC companies pulled ahead of device technology roadmaps (minimum linewidth shrink rates) to better utilize silicon surface real estate. Tremendous growth in wireless and Internet applications has driven 200- and 300mm wafer technologies to 0.18µm geometries and below, many of which incorporate complex single chip/system-on-a-chip solutions. To support these demanding device performance levels and fab yield targets, epi wafers have been favored over PW because of their reduced defect densities, gettering features, electrical properties (e.g., latch-up), and ease of manufacturing. Epi offers device manufacturers a logical pathway to transition from 200- to 300mm and avoid costly (time and money) process and design changes.
Figure 2. Epi applications market share, 2000, 2005. Numbers do not include buried layer products. |
While technologies converge toward increasing epi solutions, recent market conditions have created a tenuous supply scenario to satisfy this growing appetite for CMOS epi. Prior to 1996, epi commanded a significant price premium relative to polished wafers, which inhibited its selection as IC starting material. Responding to the mid-90s wafer shortage, silicon wafer manufacturers embarked on significant capacity expansions that were interrupted by the industry downturn between 1996-1998. This generated an oversupply situation that resulted in drastic wafer price reductions of more than 50% within a 2-3 year period. Dramatic loss in revenue, coupled with an inability to reduce costs in step with price reductions, forced wafer manufacturers to take stringent cost measures that included closing facilities, canceling or reducing capital expansion plans, delaying 300mm programs, and cutting R&D spending significantly. In 1996, wafer manufacturers invested ~55% of their revenue in capacity expansion; by 2000 this had been reduced to <10% [2].
These market pressures forced wafer manufacturers to reduce the price premium for epi, causing many IC manufacturers to evaluate plans for converting 150- and 200mm PW products over to epi, which allowed them to benefit from the cost-of-ownership/performance advantages epi offers. Year 2000 200mm epi wafer prices were roughly 20-30% higher than those for polished wafers; this is down from a 50% premium garnered by epi in the mid-90s [3].
Figure 3. High and low growth projections for 200mm wafer demand. |
Although the IC market has been growing steadily over the past two years, wafer manufacturers have been unable to spend capital for additional capacity and as a result, wafer demand appears to have outpaced available supply. With wafer forecasts showing a healthy outlook, serious questions arise as to whether the needed wafer capacity/support will be available. Many PW solutions for next-generation 200- and 300mm products require new crystal processes that have greatly reduced growth yields and diminished throughput. Increasing IC technology and device requirements (device minimum linewidth shrinks, defect densities, gettering, crystal originated pits [COPs]) have clashed with the reality of limited or lack of cost-effective wafer solutions, thereby placing polished and epi wafers at the crossroads. PW alternatives include hydrogen and argon anneals; viability of each of these revolves around cost, manufacturability, and product performance. Epi wafers require high-throughput crystal processes that enable wafer manufacturers to expand current substrate production with minimal to no equipment additions. Wafer manufacturers (Toshiba Ceramics, Shin-Etsu Handotai, MEMC Electronic Materials, Wacker Siltronic) have offered several new epi approaches to address COP and gettering concerns, while trying to manage cost and throughput considerations.
Possible roadblocks to epi adoption
Semiconductor market predictions are difficult to make due to the industry's cyclicality and volatility. Similarly, predictions of CMOS epi growth may be affected by several events. These might include the following:
- Prolonged market softening or downturn that results in an abundance of silicon wafers. This would create revenue problems for wafer manufacturers, limiting or canceling capital expenditures for additional epi expansion. The lack of available supply and a concern for continuity may cause IC manufacturers to remain with PW. A prolonged decrease in wireless- or Internet-related demand would translate into reduced need for epi.
- No cost-of-ownership advantages demonstrated by epi; no yield or performance benefits derived from epi, relative to PW, to warrant a higher acquisition cost.
- Successful PW solutions on next-generation, 200- and 300mm products that avoid the need for epi.
Future market
Though market indicators hint at softening, lasting impact on epi products is expected to be minimal. With 200mm supply/demand reaching a balance in 3Q00, any market growth during 2001 results in demand exceeding supply. What is uncertain is the extent of the forthcoming wafer shortage. The reluctance or inability of wafer manufacturers to install additional capacity (including epitaxial production) results in a tighter epi supply. Production seems to remain short of demand.
Projections on 200mm wafer demand show required capacity expansions by 2005 (relative to the year 2000 level) range from 40-60% (7-8 million/month) up to 100% (10 million/month) [3-5] (Fig. 3). During this period, 200mm epi share grows from 38% to 50+%; wafer starts on 300mm are expected to be ~70% epi.
Many of today's high-growth products rely on epi solutions for performance requirements. Need for single wafer epi production is more complicated as advanced discrete (150mm) and leading-edge 150-/200mm products fight over limited capacity. Assuming epi proves superior in CoO relative to advanced PW solutions (e.g., hydrogen and argon anneals), its position is solidified as the material of choice for next-generation, 200- and 300mm products. In summary, epi's future reflects strong growth, limited only by availability.
References
- "Si Wafer Market," Dataquest, Dec. 18, 2000.
- "Once Bitten," Electronic News, Sept. 25, 2000.
- "Silicon Wafer Market Outlook," Semicon/West, Dataquest, July 2000.
- "Wafer Vendors Warn of Scarce Raw Silicon," EE Times, March 6, 2000.
- "200mm Wafer Market Outlook," Dataquest, March 20, 2001.
Robert Royalty is worldwide sales manager at GlobiTech Inc., 1414 West Houston Street, Sherman, TX 75092; ph 903/891-9966, fax 903/870-0625, e-mail [email protected].