SEMICON West 2001 Preview
06/01/2001
July 16-20, SEMICON West 2001 Preview
EXPOSITION SHOW HOURS
San Francisco
Monday, July 16, 10:00 am - 6:00 pm
Tuesday, July 17, 10:00 am - 6:00 pm
Wednesday, July 18, 10:00 am - 4:00 pm
San Jose
Wednesday, July 18, 10:00 - 6:00 pm
Thursday, July 19, 10:00am - 6:00 pm
Friday, July 20, 10:00am - 4:00 pm
This year's Semicon West tackles the industry's evolving technology challenges through comprehensive program offerings. Whether it's an introductory course on wafer fabs or a briefing on the International Technology Roadmap for Semiconductors, Semicon West 31st's annual conference promises to address the varied needs of professionals in the semiconductor industry.
New this year are the Semi Technical Symposia — Innovations in Semiconductor Manufacturing to be held in San Francisco, and Innovations in Test, Assembly, and Packaging to be held in San Jose.
Wafer processing will be the theme in San Francisco; in San Jose, the focus will be on final manufacturing — test, assembly, and packaging. In San Francisco, events will be concentrated in the Moscone Convention Center and the San Francisco Marriott. For those attending events in San Jose, seminars and workshops will be held in the Fairmont Hotel as well as the San Jose Convention Center. Events begin Thursday, July 12, and continue through Friday, July 20.
The exhibition at San Francisco's Moscone Center runs from July 16-18.
The exhibition at the San Jose Convention Center runs from July 18-20.
 San Francisco Convention & Visitors Bureau |
To check for availability of courses or to register on-line, visit the Semi web site at www.semi.org/semiconwest. Early registration is encouraged for best selection. If you preregister for a program or event, you will automatically receive a badge allowing you to enter the exhibition. For more information, contact Semi at ph 408/943-6901 or toll free at 877/746-7788.
Registration fees for the events are listed with each entry. All fees refer to registration after July 9; before July 9, fees are lower. Keep in mind that dates, times, and venues may change. For up-to-the-minute information, check the Semi web site or visit the Semi booths at the show.
What follows is a list of 1) technical symposia and their locations in San Francisco and San Jose; 2) Standards Technical Education programs (STEPs); 3) business and education programs; and 4) Semi International Standards Meetings and Workshops information.
Technical Symposium
San Francisco
Innovations in Semiconductor Manufacturing—10 sessions
Monday, July 16-Wednesday, July 18, 8:00 am-5:00 pm
San Francisco Marriott Hotel
This symposium provides accelerated learning for semiconductor industry professionals, allowing them to define curriculum based on specific individual needs. Sessions have been developed by a committee of industry professionals and cover the latest technology trends and issues.
Registration: $595; includes admission to all sessions, which are interchangeable.
Monday, July 16
Session 101: EHS Part 1 —New Treatment Technologies
8:00-11:00 am
This session will discuss the use of copper and other metals that are expanding into the fabrication process, and how the wastes from these processes need to be treated, along with global warming emissions that must be eliminated. Topics will include treatments for copper, low-k materials, and CVD processes.
Session 102: Innovations in Interconnect Technology
8:00-11:00 am
Major device manufacturers have recently announced interconnect implementation plans for making 130nm devices. This session will review the critical issues involved in selecting the optimum low-k dielectric material and integrating it with new metallization processes.
Session 103: EHS Part 2— Challenges/Analytical Methodologies
2:00-5:00 pm
The International Technology Roadmap for Semiconductors (ITRS) has identified some aggressive targets for waste reduction and resource conservation. Alternative chemistries are identified as potential solutions. Speakers will discuss several options to address these challenges and the methodologies to identify and quantify the by-products of emissions.
Session 104: Innovations in Substrate Technology
2:00-5:00 pm
This session of Semi's technical symposium on innovations addresses the substrate requirements for the current generation of devices and explores the advances needed to support future work in this area. Challenges for silicon, silico-germanium, silicon on insulator, and gallium arsenide (GaAs) substrates will be discussed.
Tuesday, July 17
Session 105: CFM Part 1: Gases, Fluid Delivery, and Aluminum-Copper Protocol
8:00-11:00 am
In this session, papers will deal with some of the most important issues of contamination-free manufacturing. Insight on gases and gas delivery will be offered, while other papers will deal with trace metal contamination from delivery systems, on wafer surfaces, and with the protocols needed to run copper and aluminum metallization in the same fab.
Session 106: CMP Part 1: Suppliers' Perspectives
8:00-11:00 am
Chief technologists from the major manufacturers of equipment and materials for CMP processing will describe the challenges and opportunities outlined in the ITRS and how their companies are planning to meet them. A panel discussion concerning the issues facing CMP suppliers will follow.
Session 107: CFM Part 2: Liquid Chemicals and Wafer Surfaces
2:00-5:00 pm
In this session, innovative methods for cleaning wafers, managing copper plating, and monitoring contamination in DI water and on the backside of wafers will be presented. Papers discussing new techniques for characterizing and grouping defects on wafers will be given.
Session 108: CMP Part 2: Technology for ULSI Manufacturing
2:00-5:00 pm
CMP has become an enabling technology for state-of-the-art device manufacturing. This session will describe how the technical challenges are being met in the development of consumables, as well as in process modeling, control, characterization, and integration.
Wednesday, July 18
Session 109: Gas Delivery and Analysis
8:00-11:00 am
This session deals with issues of accurately monitoring and controlling the flows and impurity levels in gases. Papers will also deal with systems for safely delivering silane, filtering phosphine, and adding controlled amounts of water vapor as needed by advanced wafer processes.
Session 110: Developments in Plasma Etching and CVD
8:00-11:00 am
This session focuses on advances in production equipment and processing techniques for plasma and conventional etching and CVD. Papers will cover advanced etch technology, processes for copper and gate stack deposition, control of amorphous and polysilicon deposition, as well as plasma-assisted effluent abatement.
Innovations in Test, Assembly, and Packaging—4 sessions
Wednesday, July 18-Thursday, July 19, 8:00 am-5:00 pm
Fairmont Hotel
This symposium provides accelerated learning for semiconductor industry professionals, allowing participants to define their own curriculum based on specific, individual needs. Topic sessions have been developed and approved by a committee of industry professionals, and cover the latest technology trends and issues faced in a professional's everyday work environment.
Registration fee: $595. Registration includes admission to all sessions. Sessions are interchangeable.
Wednesday, July 18
Session 201: IC Packaging Materials and Assembly Process
8:00-11:00 am
This session focuses on key issues related to the physical design for IC packaging as well as materials, processes, and electrical characterization for single and multiple die package technologies. Topics will include die attachment, ultra-fine pitch wire bonding, die bumping for flip chip, and encapsulation. Speakers will address lead-free soldering and the impact of converting to alternative Pb-free attachment alloys. They will also discuss how these materials may affect performance and product reliability.
Session 202: Reliability of CSPs and Advanced Packages
2:00-5:00 pm
Reliability has now become even more critical for miniature packages as their size and pitch rapidly decreases, introducing fragile joints for carrying both electrical and mechanical loading. In this session, reliability test results for package technology from BGA to CSPs for a range of applications including wireless and optics will be presented.
Thursday, July 19
Session 203: 10th Annual MTC—Test Strategies for Bluetooth Devices
8:00-11:00 am
Bluetooth — a technology that enables computers, cell phones, and peripherals to communicate together without wires — is a topic with far-ranging implications in the semiconductor manufacturing arena. This session will present issues that have been raised concerning the manufacturing of these devices, as well as potential solutions as viewed by a select group of representatives from the semiconductor manufacturers, ATE suppliers, and subcontract assembly and test industries, who will all participate in a panel discussion.
Session 204: New Inspection and Metrology Technology for Fine-Pitch Packages
2:00 pm-5:00 pm
Fine-pitch packages and CSPs have raised the requirements for better inspection and metrology. The session will cover topics such as characterization of fine-pitch wafer probing, gold ball shear testing, automation of inspection, and 3-D bump inspection. A special paper will cover MEMS-type manufacturing of wafer probes.
Standard Technical Educational Programs
All programs will be held at the San Franscisco Marriott unless otherwise noted.
Sunday, July 15
STEP: Recipe Management
1:00-5:00 pm
This STEP (Standards Technical Education Program) will introduce purpose, concepts, function, and protocol associated with a new proposed standard: Recipe and Parameter Management. Topics include recipe transfer mechanism; recipe integrity; recipe content; parameter adjustment; and 200mm and 300mm implementations.
Registration fee: $295
Monday, July 16
STEP: Semi E78—Assessment and Control of Electrostatic Discharge and Electrostatic Attraction
8:00 am-12 noon
Semi 78 defines ways to minimize the negative impact on productivity caused by static charge in semiconductor manufacturing environments and to establish electrostatic compatibility of equipment used in semiconductor manufacturing. This half-day STEP will describe Semi E78-0998 and review its use. Static charge control issues, particularly in photolithography, will be discussed, as will procedures for assuring E78 compliance of equipment.
Registration fee: $295
Wednesday, July 18
STEP: Next-generation Reticle Handling and Related Standards
1:00-5:00 pm
This program will familiarize suppliers and factory integrators with the vision for a fully integrated next-generation factory based on industry standards for reticle handling. Presenters will describe how current standards and those in development are designed to work together in a highly integrated factory with automated material-handling systems.
Registration fee: $295
Thursday, July 19
STEP: Semi E10 and E79—Measurement and Management of Equipment RAM Productivity
8:00 am-12 noon
Semi Standards E10 and E79 define the metrics and calculations for the measurement of equipment reliability, availability, and maintainability (RAM) and productivity. These documents have been the focus of considerable discussion and revision since their publication. This half-day STEP will describe these standards and review their use. A workshop titled "Measuring and Managing Equipment Performance" will follow from 1:00-4:30 pm.
Registration fee: $295
Development of Metrics for the Measurement and Management of Fab-level Productivity
1:00-4:30 pm
This workshop will review understanding and experience with productivity standards, as well as gain buy-in of these documents and participation in their ongoing development. The session will also determine if and how these and related Semi standards should be revised to better suit the needs of the industry.
Registration fee: $75
STEP: Semi G79 and G80—Analysis and Assessment for Overall Digital Timing Accuracy
1:00-5:00 pm
San Jose Convention Center
This STEP will detail Semi G79 and Semi G80, a complementary set of standards. Semi G79 is an AC timing specification defined for digital ATE (automatic test equipment). Semi G80 is a test method that outlines a standard process for any digital ATE system to be evaluated for parameters that make up an AC timing specification modeled after Semi G79.
Registration fee: $295
Business and Education Programs
Semiconductor Processing Technology
Thursday, July 12-Saturday, July 14, 8:00 am-5:00 pm
Moscone Convention Center, San Francisco
Wednesday, July 18-Friday, July 20, 8:00 am-5:00 pm
Fairmont Hotel, San Jose
Having an understanding of semiconductor processing technology is a must. This introductory course will familiarize particpants with wafer fabs and address a range of topics, including how to recognize key pieces of fab equipment and how they work. Case studies of actual equipment and material problems will be considered.
Registration fee: $1595
How to Successfully Manage New Product Introductions
Friday, July 13-Saturday, July 14, 8:00 am-5:00 pm
Moscone Convention Center
This two-day interactive workshop looks at the success criteria for market-driven products as well as the strategic impact a new product has on the company itself.
Registration fee: $1750
Equipment and Materials Market Briefing
Tuesday, July 17, 8:30 am-12 noon
Moscone Convention Center
Thursday, July 19, 8:30-9:30 am
San Jose Convention Center
The expanded San Francisco session and the shorter San Jose session will provide participants with the information and analysis needed to keep up with the rapidly changing semiconductor equipment and materials industries, including the most up-to-date monthly and quarterly indicators for sales and orders.
Registration fee: San Francisco, $395; San Jose, $175
Understanding and Using Cost of Ownership
Tuesday, July 17, 9:00 am-5:00pm
Moscone Convention Center
Thursday, July 19, 9:00 am-5:00 pm
Fairmont Hotel, San Jose
Often required in requests for quotes, COO is growing in importance. This workshop will explore how the semiconductor industry employs COO and will provide a theoretical foundation and practical understanding of COO concepts and applications.
Registration fee: $895
Semi Chemical and Gas Manufacturing Group General Meeting
Tuesday, July 17, 10:00 am-12:30 pm
San Francisco Marriott
The Chemical and Gas Manufacturers Group (CGMG) is a Semi-sponsored special interest group for Semi members who supply chemicals, gases, resists, and related products to the semiconductor industry. The group provides a forum for its members to address issues of special importance to their segment of the semiconductor industry.
Registration fee: Free, but preregistration is required
Forecasting Techniques for the SEM Industry
Tuesday, July 17, 1:00-5:00 pm
Moscone Convention Center
This workshop trains participants to identify and predict the peaks and valleys of the silicon business cycle. Forecasts of IC demand, wafer-processing equipment sales, and test and assembly equipment sales for 2001+ will be presented and analyzed. Participants will learn practical forecasting and analysis skills for immediate implementation.
Registration fee: $375
Flat Panel Display Seminar
Tuesday, July 17, 1:00-5:00 pm
Moscone Convention Center
Flat Panel Displays (FPDs) have become the display of choice for product designers, and increased adoption of low-temperature polysilicon (LTPS) processes is constantly improving the quality of LCDs. This seminar will offer an overview and forecasts of the FPD device and capital equipment markets by application and technology. Participants will also learn about technology trends in LTPS manufacturing and market trends for FPD process equipment.
Registration fee: $295
Developing a Highly Skilled Work Force in Your Company
Tuesday, July 17, 3:00-5:00 pm
Moscone Convention Center
Developing a highly skilled work force for the semiconductor manufacturing industry, its suppliers, and customers is a priority. This program will highlight electronically delivered training modules currently developed for trainers and designed for technician-level training.
Registration fee: $50
EHS Interest Group Meeting
Tuesday, July 17, 3:00-6:00 pm
San Francisco Marriott
Integrating technology and even modules from multiple suppliers into a single tool is common. Sharply increased customer expectations for EHS performance and documentation, however, have left many struggling with how to efficiently divide and coordinate EHS design and documentation on these hybrid tools. This program will briefly examine the many EHS requirements and then offer detailed perspectives and solutions from both small and large suppliers, integrators, device makers, and third parties.
Registration fee: No charge (Register early because space is limited.)
2001 International Technology Roadmap for Semiconductors (ITRS) Conference
Wednesday, July 18, 8:30 am-5:45 pm
San Francisco Marriott
Twelve technology working groups will present the draft of the International Technology Roadmap for Semiconductors (ITRS), 2001 edition. Participants will learn about global technology requirements and areas for potential innovations.
Registration fee: $350
Wafer Level Packaging Workshop
Thursday, July 19, 8:30 am-5:00 pm
Fairmont Hotel, San Jose
This workshop will give an overview of current trends in the market and technology for wafer-level packaging and wafer bump bonding. It will introduce different approaches for wafer-level CSP and explain in detail process challenges and current equipment trends.
Registration fee: $395
Sunday, July 15-Thursday, July 19
San Francisco Marriott
Wednesday, July 18-Thursday, July 19
San Jose Convention Center
The International Standards Program, one of the key services offered by Semi for the semiconductor and flat panel display industries, operates as a neutral forum for the exchange of information among suppliers and users, resulting in the production of timely and technically accurate specifications and other standards of economic importance to the industry.
More than 150 committees, subcommittees, and task forces are planning to meet. For current information on Standards Meetings, visit www.semi.org (International Standards), or call Araceli Gomez at 408/943-7035 to have a current schedule faxed to you.
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SEMICON West 2001 PRODUCT PREVIEW
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Ion implantation system
The Quantum ion implantation system addresses the productivity and control issues that arise when forming source/drain structures at <0.13µm geometries. The system employs a beamline that optimizes efficient transport of low-energy ion beams. A new extraction technology and differential lens provide ultralow-energy beam currents and deliver high throughput and accuracy for source/drain and extension implants. Quantum also incorporates high accuracy power supplies for the extraction, mass analysis, and differential energy systems. An independent total energy monitor provides independent interlocking capability that, when used in differential mode, can provide closed-loop control of the total implant energy accuracy to within 10V for ultralow-energy implants. Applied Materials Inc., Santa Clara, CA; ph 408/748-5227 or 408/563-0647, www.appliedmaterials.com.
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X-ray diffraction analyzer
The DCD Pro X-ray Diffraction Analyzer brings fast, automated X-ray analysis to the production environment. Capable of measuring thickness and composition of epitaxial layers just a few atoms thick, the instrument is highly suitable for the study of SiGe structures as well as HBT, III-V, II-VI, GaN and HEMT devices. The dynamic range of the entire system is >5 orders of magnitude, allowing accurate measurement of both strong substrate peaks and weak diffracting peaks arising for very thin layers. Cassette-to-cassette capability and powerful software provide high throughput and easy integration into the production line. Philips Analytical, EA Almelo, The Netherlands; ph 31/546-534-386, [email protected], www.analytical.philips.com.
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Wet oxidation RTP tool
The 3000 is an advanced RTP tool available with dual side heating to minimize pattern-induced thermal nonuniformity and to achieve ramp rates up to 250°C/sec. It is a bridge tool that can be configured for both 200mm and 300mm wafer systems. It uses a linear array of tungsten halogen lamps above and below the wafer, with individual lamp control. In conjunction with a proprietary wafer-rotation design, this allows temperature uniformity better than ±2°C, all points, all wafers. The 3000 Steam is an advanced wet oxidation RTP tool designed for volume production of devices <0.18µm. Based on the 3000 and STEAMpulse systems, 3000 Steam provides extended processing capabilities. It features an ex situ steam generator that provides good process results and repeatability. Mattson Technology, Fremont, CA; ph 510/657-5900 or 800/628-8766, www.mattson.com.
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300mm load port
Fixload is a load port for 300mm wafer manufacturing equipment that is part of this company's "Comprehensive Clean Concept," a methodology that allows Fixload to achieve the cleanest possible wafer-processing environment. The interoperable system provides the fastest available open/close time for FOUP doors, is easily accessed, and is Semi-compliant. Fixload provides a quick release function and allows poly-dimensional adjustment to the tool. Options include the FixMAP carrier mapping system for detecting misplaced wafers in a FOUP. With FixMAP, mapping occurs instantaneously and independently of door or handler motion. Brooks Automation, Jena, Germany; ph 49/3641-64-4000, www.brooks.com.
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RTP furnace
The Xcelerate Furnace-RTP provides single-wafer flexibility with furnace productivity. The vertical cluster architecture and side-by-side installation give Xcelerate the smallest footprint in its class. Four independent process chambers provide high throughput and allow sequential processing. The hot-wall isothermal process chambers give superior temperature control and eliminate emissivity problems. Chlorine compatibility with the quartz chamber yields high GOI and ensures low metals. Wet and dry oxides are grown with very good uniformities and no "continental drift." CVD applications include silicon nitride, oxynitride, HTO, and amorphous/polysilicon. The single-wafer furnace platform affords lower COO and provides thermal process performance for next-generation gate dielectrics. Specifications of the system include the following. Thin oxidation: thickness of 15Å, uniformity of 0.75% (1s), no continental drift, and throughput of 120 wph. Thin silicon nitride: thickness of 20Å, uniformity of 0.75% (1s), no micro-depletion, and throughput of 120 wph. Silicon Valley Group, San Jose, CA; ph 831/439-6407, [email protected], www.svg.com.
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Inspection and review system
The redesigned Axiospect 300 inspection and review system now features an increased throughput in combination with a decreased footprint. The system offers state-of-the-art optical imaging techniques, including UV live imaging and the white light confocal (CSM) with this company's Chromat C technology. The advanced macro unit enables front, back and edge inspection all on one unit. The wafer is held at eight points at the edge and only has to be loaded once to perform all macro inspection tasks. The software option ADC adds safety and repeatability to advanced defect classification applications. System specifications include: throughput up to 150 wafers/hr; resolution down to 100nm; macro unit with cardanic suspension; footprint of 4.16 m2, including macro and operator; and UV (248 and 365nm), CSM (confocal), differential interference contrast, darkfield and brightfield, all on one system. Carl Zeiss Jena GmbH, Jena, Germany; ph 49/3641-6420-44, fax 49/3641-6429-38, [email protected], www.zeiss.de/semiconductor.
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Plasma etch systems
The Omega 201+ is an enhanced version of the Omega 201 with additional features and functionality, including a Windows NT operating system, optional cool down and aligner positions, and overall reduced footprint. It offers leading plasma source technologies, including PERIE, ICP and M0RI. Omega 201+ continues to offer advanced technology features within the Omega 201 package of high performance combined with low footprint and costs. The Omega fxP expands this company's etch capability beyond the Omega 201 single-chamber concept into multi-chambered cluster etch technology. Based on the field-proven fxP cluster platform, Omega fxP combines standard Omega etch plasma sources, such as ICP, PERIE and MORI, with the Brooks MX 800 handler. Customers are now offered both advanced sequential etch or very high-throughput, parallel etch processing. Benefits include access to this company's extensive etch process library, easy process transfer from existing Omega 201, and spares and training in common with fxP-based CVD and PVD technologies. Trikon Technologies, Newport, UK; ph 44/1633-414000, [email protected], www.trikon.com.
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5-station track system
The Tractrix 5-Station Spin Track System may be configured as a coater or as a developer. Up to three hot plate modules make suit it for curing specialized resists and coatings such as inter-layer dielectric (ILD) material. As a developer, the Tractrix 5-Station tool can accommodate post-exposure and post-develop baking with chill. The system also features automatic spin-and-bake profiling for easy spin curve generation. The tool provides a cost-effective spin track solution within a 19 x 81-in. footprint. Ideal for processing substrates ranging in size from 3-8 in., the system features easy operation (icon-driven, Windows-based, touch-screen display), low-maintenance design, optional LAN connection, and low cost of ownership. SITE Services Inc., Santa Clara, CA; ph 480/585-2526 fax 480/585-2544, [email protected].
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Single-wafer cleaning system
The Goldfinger Mach series of critical-feature, single-wafer cleaning systems is designed for post-etch cleans, pre-deposition cleans, and via cleans for 150-70nm generation geometries for either 200mm or 300mm wafers. Goldfinger Mach 1 is the first in the series. At 150nm and smaller geometries, particle removal from critical features such as gate stacks, bit lines, and vias has challenged traditional cleaning technologies. Chipmakers are experiencing yield losses due to incomplete cleaning and circuit damage. By combining new, single-wafer megasonic technology with advanced process and wafer drying technologies, the Goldfinger Mach process provides a solution to these challenges. It removes particles from these ultrafine geometries without damage. The Goldfinger Mach 1 platform houses a single process chamber with the patented Goldfinger megasonic, on-demand injection from single or multiple chemistry sources, independent top and bottom process control, and the integrated Sahara surface tension gradient drying process. The system enclosure is 23 ft2 and can be bay-and-chase or ballroom installed. It has an E.15 compliant load port that — along with the system's robotics — can be fitted for 200mm cassette, 200mm SMIF, or 300mm FOUP use. It is well-suited to development and pilot line environments because of its smaller-volume package. Verteq, Santa Ana, CA; ph 714/445-2000, fax 714/445-2204, [email protected].
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Damascene metal plating
The Damascene Metal Plating (DMP) system is designed for high-quality plating of copper on a compact-footprint platform (based on the field-proven CMP model). DMP exceeds today's application requirements with throughput as high as 70 wafers/hr. The system offers dry in/dry out, uniform plating on copper damascene structures. Edge, bevel and backside cleaning are integral to the tool, which features a guarantee of >250 hrs MTBF and <2 hrs MTTR. The DMP system integrates well with any PVD or CVD deposited barrier and seed. Some features of the system are an isolated cleaning area layout, two cassettes C to C, 4-bath multiplating, chemical cleaning, and edge etching. EBARA Technologies Inc., Sacramento, CA; ph 916/920-5451, [email protected], www.ebaratech.com.
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300mm FOUP
The OEM300i load port has a simple, modular design that is light and compact, with a small form factor and low cost. It provides fast wafer access time and does not require preventive maintenance or set-up adjustments. Features include simple plug-and-play installation, compact space-saving design, light weight, BOLTS/Light (standard) and BOLTS/M (optional), with pinch bar, FEOL and BCOL pins. The unit is available in a durable powder coated finish or in polished stainless steel. AJS Automation, Ipswich, MA; ph 978/356-7303, fax 978/356-7554, [email protected].
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3D wafer bump inspection system
The 3Di-8000 is designed for high-speed bump and wafer inspection. The system incorporates this company's 3D Rapid Confocal Sensor, with proprietary 2D bump and active die inspection technologies to provide manufacturers with high speed and high accuracy combined in a single bump inspection solution. The system quickly and accurately measures the height and coplanarity of solder and gold bumps (also called wafer level interconnects), which provide the critical electrical connection between the die and a package or circuit board. In addition, the 3Di-8000 incorporates 2D inspection capabilities for characteristics such as bump placement and size, as well as active die area inspection. The system can inspect wafers from 75-300mm, bridging the transition to larger wafer sizes. The 3Di-8000 is a complete 3D inspection solution that combines high-speed and a proven accuracy to <2µm. While meeting existing requirements, the 3Di-8000 has also been designed with scalability in mind in order to meet the growing needs of new and emerging markets such as optoelectronics, MEMS, and other micro structures. August Technology, Bloomington, MN; ph 952/820-0080, [email protected], www.augusttech.com.
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Moisture and oxygen contamination monitoring
Trace moisture and oxygen contamination leads to oxidation, particle formation, and variable layer characteristics, directly affecting yield and productivity. The FabSense H2O-3000 moisture event sensor provides continuous, real-time monitoring of UHP inert gas supplies to critical processes such as PVD, etch and epitaxy. It ensures gas specification to the point of use and rapidly alerts the user in the event of moisture ingress — >20 ppb moisture can be detected in <1 min. Moisture and oxygen contamination within process tools can be monitored using the FabSense H2O-3000V and O2 Vac sensors. These sensors, designed for direct on-tool mounting, operate from atmospheric pressure to the ultimate vacuum of the system and provide continuous measurement of the partial pressures of moisture and oxygen in the tool environment. The sensors can be integrated easily into the FabSuite Network Monitoring package and industry-standard SCADA systems. BOC Edwards, Wilmington, MA; ph 800/848-9800, [email protected], www.bocedwards.com.
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Wafer inspection system
WIN-WIN 50 is a high-performance wafer inspection system for use with the 150-100nm generation of devices. It is an optical image comparison system that incorporates confocal imaging with a UV light source. While the UV light provides higher resolution for defect detection, the confocal effect provides the ability to focus on the top or bottom features and suppresses background noise. WIN-WIN 50 is based on leading-edge technologies such as a hybrid microscope, a high-speed image-processing unit, and a very precise wafer stage. Specifications of the system are: sensitivity <0.1µm; false defects <1%; wafer sizes up to 300mm; detection mode — die to die/cell to cell; illumination source — UV/white light; and microscope — confocal/conventional. Accretech/TSK America, San Jose, CA; ph 408/952-7900, fax 408/952-7901, [email protected].
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"All dry" wafer and device cleaning
The Eco-Snow process features a precisely controlled, fast-moving stream of dry, solid carbon dioxide (CO2) "snow" particles and CO2 gas generated through a specially designed nozzle. The process is contained in a Class 1 minienvironment and is available in automated and semi-automated models. Eco-Snow's process offers advantages over conventional "wet" methods, including: elimination of spin rinse drying, removal of particulates down to <0.1µm, and environmental compatibility that requires no special operating permits. Applications include post-CMP, GaAs full metal liftoff and post-metal liftoff, CCD Array pre- and post-wire bond, and optical filters and devices on Gelpaks or tape hoops. Eco-Snow Systems Inc., Livermore, CA; ph 925/606-2000 ext 311, [email protected], www.eco-snow.com.
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CMP slurry or chemical blending and delivery
These PLC-operated systems can be used for CMP slurry or for chemical blending. They have a drain hole and gravity flow technique that gives repeated mixtures <0.2% and can mix ratios as high as 200:1 with volumes as low as 20cc. Systems can deliver chemical mixtures as low as several ounces, or up to 5 gpm. Delivery can be to a supply loop or directly to a point of use. The new mixing and delivery system is basic and is designed with no pumps or scales that need attention. It is a simple pressure and gravity feed system, designed with conservation in mind, which can supply chemicals to one or more points of use. Due to its simplicity, system costs are low. The slurry or chemical mixture that is required is preset for the POU or supply loop, allowing the user to set the exact volume that is needed. The system can be set up with a feedback loop that can cycle slurry or chemicals to keep them mixed and ready. Several models have a storage tote that can be filled with only the amount of chemicals that are needed for a day, or a week, thus eliminating waste. At present there are four models: the CFA, CFB, CFC and the CFD. They are 5 gpm, 2 gpm and a 2 lpm chemical delivery systems. The CFD is a small volume point of use (POU) system that will mix and then serve an individual unit. ChemFlow Systems, San Jose, CA; ph 408-441-6575, www.ChemFlowSys.com.
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Structural process management tools
IC3D 845 and 875 DualBeam FIB/SEM tools deliver advanced 3D metrology for in-fab structural process control requirements. The first fully automated and completely integrated 3D metrology system is designed to facilitate the transition to 130nm nodes in semiconductor design and manufacturing. The IC3D systems combine in-situ FIB milling and SEM imaging with automated wafer handling and a powerful and flexible metrology package to provide rapid access to data. The Expida 1265 is a fully automated DualBeam Structural Diagnostics tool for pre-fab process qualification and in-fab characterization and analysis of process excursions and defects. It allows users to cut, view, measure, and analyze the structures of ICs during all aspects of manufacturing. Its high-performance stage can move between locations at speeds up to 100mm/sec, while maintaining better than 1µm accuracy. Designed as a "bridge tool," the Expida can accommodate both 200 and 300mm wafers with no interruption to processes. FEI Co., Hillsboro, OR; ph 503/640-7500, fax 503/844-2615, [email protected]
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Excimer laser for FBGs
The FIBEX excimer laser writes sharp Fiber Bragg Gratings (FBGs) with easy reproducibility. It has improved spatial coherence of more than 2mm, due to its patented resonator design. It also offers a newly designed laser cavity that eliminates drift and vibration, resulting in beam pointing stability <100µrad. A stable energy discharge mechanism is incorporated to minimize energy fluctuations, improving pulse-to-pulse stability to sigma <1%. FIBEX is well suited to writing any type of grating because of its very good mechanical and optical long-term and short-term stability specifications. Its high repetition rate, 200 Hz, allows FIBEX to produce high throughput, and its proven industrial design ensures reliable operation for high or low duty-cycles, offering the flexibility to use the laser in either a production or an R&D environment. Lambda Physik Inc., Fort Lauderdale, FL; ph 954/486-1500, [email protected], www.lambdaphysik.com.
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VLSI test system
The J973EP VLSI test system features quad-site testing of system-on-chip (SOC) devices and new memory test, mixed-signal, and high-current voltage source options. It gives manufacturers of high-performance devices the flexibility to shift between structural and full-performance test, or to balance both types of test, in order to minimize costs. Manufacturers of microprocessors, core logic, integrated processors, and graphic devices can increase frequency, accuracy, timing edgesets, and pattern memory performance. Chipmakers and subcontrators can maintain a test system platform that is capable of meeting long-term digital test needs while also meeting an occasional or temporary need that results from testing a large variety of devices. Teradyne Inc., Munich, Germany; ph 818/874-7310, [email protected], www.teradyne.com
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POC and Si-O contaminant monitoring
Molecular contamination monitoring at 248nm requires that compounds such as amines, ammonia, and NMP be continuously measured to ensure filter life and to guarantee resist uniformity. The contamination challenges of 193nm and — in the future —157nm lithography are much greater. In addition to the monitoring needed to protect the development of chemically activated resists, there are airborne contaminants that can deposit on the optical lens surfaces and reduce laser throughput at 193 and 157nm. These new compounds fall loosely into two categories: photochemical organic contaminants (POCs) and silicones/siloxanes (Si-O). Sources of such contaminants include construction materials within the fab and tools, incoming purge air and nitrogen gas sources, and the outgassing of the photoresist itself. The AirSentry II POC/Si-O monitor has an internal calibration system based on permeation devices for the compounds of interest. Multipoint sampling from 16, 30 or 45 sample points is possible with rotary sampling valves mounted within the system. AirSentry II can be combined with this company's AirSentry-IMS system to give monitoring capability for total amines, ammonia, NMP, POCs, and Si-Os from one monitoring system. Molecular Analytics Inc., Sparks, MD; ph 410/472-2146, fax 410/472-2156, [email protected]