Japanese companies design multifunction minifab tools*
06/01/2001
Katsuya Okumura, Yu-ichi Mikata, Kyoichi Suguro, Yoshitaka Tsunashima, Ayako Shimazaki, Toshiba Corp. Semiconductor Co., Process and Manufacturing Engineering Center, Tokyo, Japan
*This article has been translated for SST from the March 2001 issue of Nikkei Microdevices, our partner in Japan.
overview
Toshiba, TEL, and a new Japanese national project aim to come up with a better way to quickly turn out small volumes of complex systems chips at low cost, by rethinking the entire semiconductor production process. Their proposed minifab replaces conventional lithography, deposition, and traditional cleanroom management with direct-write stencil ion implantation, multipurpose fast thermal processing, scan coating, immersion plating, and controlled-environment boxes.
With ever shorter product life cycles, chipmakers need to develop and produce semiconductors with faster turnaround time. Producers must react nimbly to changing conditions, so they need to do flexible, small-lot production. Here we map out our full plan for the technologies and equipment required for such a minifab.
First, the minifab will process wafers in batches of 25. This is the most reasonable number of wafers that can be exposed with good results before having to readjust the exposure tool. Since exposure is the most costly process, it's sensible to choose a batch size that optimizes exposure results. All other equipment will also use this standard batch size, so wafers can flow uniformly through the whole process.
Then, for fast, flexible production, the minifab will need multifunctional equipment. The raw process time for each process must be short; each tool should be able to do several processes, and fewer tools should be required on the production line.
Fast multifunctional thermal processing
One example of such multifunctional equipment is the new fast thermal processor we've developed with Tokyo Electron Ltd. (Fig. 1). Currently, most high-heat processes like oxidation, diffusion, and chemical vapor deposition take four to five hours, so the tools process large batches of wafers at once to improve throughput and reduce costs. This new processor instead handles only 25 wafers at once, but heats up and cools down much faster to process them in only one hour, getting the same throughput in a manner better suited to small, flexible production runs. TEL says the heater module is made with a new material and a new structure, so it heats up at 200°C/min, compared to about 15°C/min for conventional equipment, and cools down at 75°C/min compared to 10°C/min. Running the smaller batch also reportedly allows more even heat distribution for better deposition.
 Figure 1. Sketch of a multifunction fast thermal processor. |
This processor also gets to vacuum pressure faster than conventional equipment, thanks to a special wide-area pressure control valve, which manages both isolation and opening, and can control pressures ranging from <1torr to several hundred torr. Once the processor has reached vacuum, a small in-line analyzer checks immediately for leaks, eliminating the usual delay. A special gas injector helps the system return quickly to atmospheric pressure by pouring in lots of nitrogen without scattering particles within the chamber (see table on p. 000).
So that this heat processor can be used for several different processes, its gas supply comes in integrated modules instead of the usual supply lines. Thus, the gas can be switched in a matter of minutes instead of days. And it includes a dry cleaning system that cleans out the chamber with gas, so it can be used for a different process without cross-contamination.
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With these flexible features, this heat-processing unit should be able to combine several usually separate process steps, such as oxidation-SiN deposition-SiO2 deposition; SiO2-SiN-SiO2; or Ta2O5 deposition-annealing.
Stencil mask ion implantation
Key to reducing process time and cost with small runs of complex system chips is replacing conventional masks and lithography with direct ion implantation through a stencil mask. A complex system chip may have up to 10 or so different types of pn junctions, from sources and drains to wells and channels, each one requiring resist coating, exposure, developing, inspection, ion implantation, and resist removal. Repeating these steps 10 times may account for 15% of total raw process time and 10% of total cost. When finer geometries need excimer lasers, the costs will go up more.
But implanting ions directly through a stencil could eliminate the resist processing steps, potentially reducing the time it takes to make the pn junctions from four hours to one, and cutting the cost in half. Replacing all the resist and lithography equipment with one ion implanter also cuts down needed cleanroom space by about 2/3. And stencil mask ion implantation would allow the quick changeover of small product runs needed for an efficient minifab.
 Figure 2. A stencil ion implanter. The wafer is placed on a stage that moves in the x-y direction, and ions are implanted one chip at a time, just like with a stepper. |
Our ion implanter uses a stencil mask the same size as the wafer, patterned with holes matching the pattern desired, and positioned several dozen microns above the wafer (Fig. 2). An ion beam scans the wafer, implanting ions through the holes in the stencil. Ion type, energy, and dosage can be changed for each chip on the wafer. The scan field is 10-30mm, and the beam's parallelism is excellent, so uniformity of implantation across the surface is improved. Resolution of layered patterns can be controlled as well as in conventional lithography.
Direct-write, maskless implantation is the only solution we see for the huge cost of masks for coming generations of complex systems chips, especially small production runs. Throughput is a concern, but we are investing major resources to solve this problem.
Scan coating and immersion plating
Another important way to reduce process time and cut costs will be to eliminate plasma processes. We plan to replace plasma CVD processes for making insulating layers in multilayer circuits with scan-coating equipment, which we have described previously. Scan coating is much cheaper than CVD, and uses only a tenth of the material that spin coating uses.
For metal-plating processes, we've developed an immersion plating technology, which we have also described before. A porous ceramic on the front of the anode effectively increases the resistance of the plating solution and makes a much thinner and more uniform coating, cutting use of plating solution down to 1/10, and the size of the equipment down to 1/3.
Controlled-environment boxes
To protect the wafers from contamination from these multiprocess tools co-located in one large room, the wafers will move about the minifab in controlled-environment boxes (Fig. 3). These closed-system carriers use a built-in fan to force air through a particulate filter and a chemical filter, removing contaminants from the cleanroom air, and harmful gases emitted by the wafer itself after processing. A few minutes of running the fan motor reduces the concentration of NH3 from 120µg/m3 to below detectable levels. After the fan motor stops, the level does not increase for 150 min.
 Figure 3. A controlled environment box. |
This controlled-environment box also removes moisture, so it can prevent corrosion of aluminum circuits. Seven days after RIE processing, wafers stored in a conventional carrier had 150 units/wafer of corrosion, while those in the new box had very few. The filter system removed impurities like Cl emitted by the wafers themselves, and controlling the moisture in the box as well reduced corrosion to essentially zero.
Using these controlled-environment boxes may reduce chemical contamination and cross-contamination, and may greatly reduce the cost of cleanrooms and wafer transport systems.
Now that we have essentially determined the key technology and basic equipment for the minifab, we will need to practice running the equipment and see if it achieves the productivity we expect from earlier simulations.
For more information, contact Katsuya Okumura at Toshiba Corp., 1-1, Shibaura 1-chome, Minato-ku, Tokyo, 105-8001, Japan; ph 81/3-3457-4511, fax 81/3-3456-1631.