Empirical-based modeling for control of CMP removal uniformity
06/01/2001
Alan Jensen, Peter Renteln, Stephen Jew, Lam Research Corp., Fremont, California
Chris Raeder, Patrick Cheung, Advanced Micro Devices Inc., Austin, Texas
overview
A method for optimizing parameters to control CMP removal rate uniformity has been developed and tested. The design-of-experiment method was used to determine empirically the sensitivity of removal rate at various wafer radii using linear belt CMP tool parameters. The recipe was determined to achieve the most uniform final profile for a given incoming film thickness profile. The model was verified on oxide and copper CMP processes, demonstrating reductions in set-up time.
 Figure 1. Linear planarization technology contains an air bearing from a circular platen that presses a moving polishing belt against an aligned rotating wafer. |
The ability of chemical mechanical polishing (CMP) to provide a uniform surface is often complicated by the nonuniformity of the deposited film. For example, chemical vapor deposition (CVD) can create center-to-edge thickness gradients, and electrodeposited copper can have edge-thick radial thickness profiles. CMP processes are typically set up to remove material at a uniform rate over the entire surface of the wafer without compensating for nonuniformity. If, however, a CMP process is set up to compensate for nonuniformity of the incoming film, the amount of over-polish required for damascene processes and final film thickness variation can be reduced, potentially improving die sort yield at the end of the line.
 Figure 2. In the six-zone air bearing platen, radial removal rate adjustments are made by changing the pressure at each zone. |
CMP
Optimization was performed using Lam's Linear Planarization Technology (LPT) on the Teres CMP system. Unlike rotary CMP, LPT uses an air bearing from a circular platen that presses a moving polishing belt against an aligned rotating wafer (Fig. 1). The wafer is held in place by a carrier and spindle. Radial uniformity control is achieved by adjusting any of six pressure zones in the air bearing platen beneath the polishing pad (Fig. 2). Radial pressure adjustment can compensate for edge-high and center-high incoming film thickness. Relative to rotary CMP, the control of uniformity from beneath the polishing pad in linear planarization provides a wider process window in terms of pad speed, pad hardness, and pressure range. The added flexibility can improve planarization length and nanotopology performance [1-3].
Nonuniformity compensation
A step-by-step method is used to understand the influence of each pressure zone and compensate for incoming nonuniformity. By adjusting the CMP removal rate in thicker or thinner regions, variations in final film thickness can be minimized. Because it is not practical to use all possible combinations of variables, the design-of-experiment (DOE) method was used to reduce significantly the number of trials required. Four steps are involved.
Film thickness measurements are first selected to capture radial nonuniformity. The influence of selected input factors (air zones) on removal rate at each radial location is then determined by DOE. Computerized statistical analysis (SAS JMP) and an iterative equation-solving program are then used to model uniformity vs. air zone pressure changes. Finally, the results are verified on test wafers.
The response surface method is used to establish a dependent response vs. radial position on the wafer. A model function is derived for removal rate (RR) at each radial point (ri):
RRri = f (Factor 1, Factor 2 ...)
Multiple linear regression analysis is then used to establish a relationship for each radial point. The equations are solved simultaneously to give a removal profile that most closely matches the incoming film. In this situation, a computer model is used.
Tuning oxide removal rate profiles
A DOE was run with air zone pressures as the input parameters and removal rates at each of 24 points (12 radii, 2 diameter scans) as the output parameters. Mean analysis of variance was used to determine the coefficients for main effects and squared terms. The interactions between pressure zones were found to be insignificant.
 Figure 3. The shapes of the removal coefficient profiles suggest that the polishing belt bends upward within an air pressure zone and downward outside the zone. |
The main effects of changing air pressure on the removal profile are plotted in Fig. 3. The removal coefficients represent the ratio of the change in removal rate (DRR in Å/min) to the change in platen air pressure (DP in lbs/in2) for each pressure zone, at each radius. Each line represents the response curve for a given pressure zone. The shapes of the removal coefficient profiles suggest that, in general, the polishing belt bends upward within an air pressure zone and bends downward outside the zone.
 Figure 4. In optimizing the oxide removal rate profile, a flat removal profile was achieved after two tuning wafers. |
The removal rate coefficients were then used to create equations for the expected removal rate at each radius. Multiplying the coefficient by the expected change and then adding the result to the initial removal rate can then determine a predicted result for the combination of all pressure zones. For the case when a flat removal profile is desired, the computer model is set up to change the input parameters to minimize the standard deviation of the expected removal rates at each radius. The results are shown in Fig. 4. The oxide removal profile on the first wafer was fast at the edge. The computer model suggested a recipe to compensate with air bearing Zones 3-6 set to 4.5, 16.4, 8.3 and 4.6 psi respectively — an unlikely suggestion without computer modeling. The first verification wafer showed that while the profile improved, there was room for further optimization. A second adjustment was made (Zone 2 lowered by 6 psi), resulting in a flat removal profile. The flat final profile was achieved after running only two tuning test wafers.
 Figure 5. An STI CMP process has been tuned by adjusting the air bearing such that the removal profile and incoming film thickness are matched. |
Damascene processes require the following steps: etching of the trenches, covering of the wafer with a film to fill the trenches, and polishing of the "up" regions while leaving the trenches filled. In the ideal case, the polish removal profile matches the incoming film thickness profile exactly, and the film clears simultaneously from all the up regions on the entire wafer. In the real world, the film on the entire wafer will not clear simultaneously, so an "overpolish" is employed to guarantee that all the up regions are cleared. The regions that clear first will be polished longer than necessary while the rest of the wafer clears. This overpolish is potentially detrimental and can result in dishing and nonuniform fill. The need for overpolish is therefore reduced when the removal profile matches the film profile, leading to corresponding reductions in dishing and thickness variation in the trenches' fill.
Figure 5 shows the results on wafers when the removal profile was tuned to match the incoming oxide profile on shallow trench isolation (STI) CMP. The y-axis is shown as normalized oxide thickness or removal. The removal profile and incoming profile match, so the oxide is effectively cleared from the nitride, resulting in a more uniform trench oxide and less need for overpolish.
 Figure 6. A decrease in copper removal rates at the edge of the wafer is shown when air pressure in Zones 1 and 2 or 3 and 4 are increased. |
Tuning copper removal rate
The overall goal of copper CMP is to remove the bulk copper (clear) from the top of the dielectric and barrier and leave behind patterned trenches filled with copper. Usually, copper electroplating has an edge thick profile (although different processes produce different profiles). A perfectly flat removal profile will clear the bulk copper in the center of the wafer first while the wafer edge requires more polishing to remove the edge copper. The center of the wafer is thus overpolished. This creates nonuniform dishing and erosion results from the center to the edge since these metrics are closely tied to the amount of overpolishing done after clearing bulk copper. Radial uniformity control allows one to match the removal profile closely to the incoming thickness profile so that the bulk copper will be cleared nearly simultaneously across the wafer radius. As with the STI process, the overpolish time is reduced, which equates to control of dishing and erosion across the wafer.
The change in copper removal profiles with respect to changes in platen zone pressure for Zones 1-4 is shown in Fig. 6. In this DOE, Zones 1 and 2 were changed together, as were Zones 3 and 4. As the air pressure is increased, the edge polishes more slowly relative to the wafer center, as in oxide removal.
Figure 7 indicates a blanket incoming thickness profile and the removal profile achieved with platen pressures of 10, 10, 1, 1, 0, and 0 psi from Zones 1-6, respectively. The removal rate at the edge of the wafer is slightly faster than is suggested by the incoming deposition profile because the platen pressures were chosen to ensure complete clearing of the copper near the wafer edge. There are some nonuniformities and inconsistencies on the wafer edge because of the electroplating profile variation and the electroplating contact points. If we had chosen to remove the copper using a process with the best WIWNU (flattest removal rate profile), the center of the wafer would have cleared first; then, after additional time, the edge would have cleared last. This would create higher dishing and erosion in the wafer center compared to the wafer edge. If residual copper or barrier remains, shorting across lines within the die will occur.
Conclusion
A method for tuning the radial removal profile of a CMP process that engineers a match to an incoming film thickness profile has been demonstrated. The relationship between key process parameters and material removal at radial positions on the wafer can be established using DOE methods and readily available statistical methods for modeling and iterative equation solving. Simulations can be run to optimize output uniformity prior to verification on wafers, saving both time and money. By applying this methodology, post-CMP wafer surface uniformity can be optimized for a wide variety of incoming films — from STI to copper — to improve device performance and die yield.
References
- D.A. Hansen, et al., "Linear Velocity and Its Effect on Planarity," 1999 Proceedings Chemical Mechanical Planarization for the ULSI Multilevel Interconnection Conference (CMP-MIC), p. 417-419.
- D. Boning, et al., "Characterization and Modeling of Nanotopography Effects on CMP," Proceedings of International CMP Symposium 2000, Tokyo, Japan.
- K.V. Ravi, "Wafer Flateness Requirements for Future Technologies," Future Fab International.
- A. Jensen, et al., "Controlling CMP Removal Rate Profiles Using Emperical Modeling," 2000 Proceedings Chemical Mechanical Planarization for the ULSI Multilevel Interconnection Conference (CMP-MIC).
Acknowledgment
Jeff Farber, who works for the Lam Research Corp., is also an author of this article.
Alan Jensen is a graduate of Willamette University. Before joining OnTrak in 1994, he worked at Wacker Siltronic as an applications engineer in post-CMP cleaners. Currently, Jensen is an applications engineering supervisor for CMP/clean.
Peter Renteln received his BS in engineering physics at U.C. Berkeley and his PhD in materials science and engineering from Cornell. He joined Lam Research Corp. in 1999 and is currently senior manager of applications. Prior to joining Lam, Renteln worked at Motorola's APRDL on copper CMP development and in CMP technology at National Semiconductor.
Stephen Jew received his BS in mechanical engineering from the California State Polytechnic University at San Luis Obispo and is currently a senior process development engineer for the CMP/Clean Process Technology Group of Lam Research Corp. Since 1997, he has worked on copper CMP research and process development.
Jeff Farber received his BS and MS degrees in mechanical engineering and his MBA from Rensselaer Polytechnic Institute. Since joining Lam Research Corp. 16 years ago, he has been in R&D of silicon wafer manufacturing technology and semiconductor characterization. Farber is the author of numerous technical articles and has been granted several US and foreign patents.
Chris Raeder received degrees in materials science and engineering — a BS from Rensselaer Polytechnic Institute in 1989, an MS from the University of Washington in 1991, and a PhD from Rensselaer Polytechnic Institute in 1995. He is a senior member of the technical staff at AMD, responsible for polish technology at AMD's Fab25.
Patrick K. Cheung received his BS degree in materials science engineering from the University of California, Berkeley in 1993. He joined AMD as a thin films manufacturing engineer before moving to CMP in 1998.