Issue



Defect reduction and improved gettering in CZ single-crystal silicon


06/01/2001







Hisashi Furuya, Kazuhiro Harada, Mitsubishi Materials Silicon Corp., Yonezawa, Yamagata, Japan
Jea-Gun Park, Hanyang University, Seoul, Korea

overview
The density and type of defects in single-crystal silicon wafers are functions of the growth rate of the crystal and the temperature gradient at the liquid/solid interface during crystal growth. Different types of defects dominate in different ranges of the input variables, and it is possible to identify a process range that minimizes the defects. This process is described. The resulting silicon wafers are evaluated and their gettering ability is discussed.

Single-crystal wafers from conventional Czochralski (CZ) silicon usually suffer from defects known as crystal originated particles or pits (COP) [1]. The COPs are grown-in agglomerations of vacancies that may cause degradation of gate oxide integrity [2], isolation leakage [3], and junction leakage [4], resulting in lower device yield.


Figure 1. A schematic graph showing the relationship between the type of grown-in defects, the concentration of intrinsic point defects, and v/G (where v is the growth rate of the crystal and G is the temperature gradient in the crystal at the solid/liquid interface).
Click here to enlarge image

It is difficult to grow CZ silicon single crystals without these grown-in octahedral defects [5] using the conventional crystal growth technology because the agglomerates of self-interstitial silicon tend to be formed at lower growth rates [6], where agglomerates of vacancies are less likely to form. In order to prevent the effect of COPs on devices, polished wafers are sometimes replaced with epitaxial wafers or hydrogen-annealed wafers, thus increasing the cost of the starting material.

A high-volume, lower-cost process was developed that produces crystals without grown-in defects, which we have termed "pure silicon." More than 100,000 wafers of pure silicon are being produced every month. In this report, the production concept, quality, and gettering ability of pure silicon are described.

Production concept
During the typical crystal growth process, three types of grown-in defects are usually formed in CZ silicon single crystals: 1) agglomerates of vacancies, 2) nuclei of oxidation induced stacking faults (OISFs), and 3) agglomerates of self-interstitial silicon. Recent investigations [7, 8] have pointed out that the formation of these grown-in defects depends on the concentration of vacancies and self-interstitials. Also, the concentration of the intrinsic point defects depends on the ratio, v/G, of the growth rate (v) of the crystal and the temperature gradient in the crystal at the solid/liquid interface (G).


Figure 2. The axial distribution of defects in a CZ silicon single crystal grown varies with v/G, which was varied along the length of the crystal in this experiment. The condition for growing pure silicon can be identified. The defects are reflected in measurements of recombination lifetime after annealing at 800°C for 4 hr and 1000°C for 16 hr.
Click here to enlarge image

The relationship between the ratio v/G and the concentration of various types of intrinsic point defects is shown in Fig. 1. The concentration of intrinsic point defects in this figure is the level just before the formation of grown-in defects. For larger v/G, the dominant intrinsic point defect is a vacancy, and for smaller v/G, it is a self-interstitial. The agglomerates of vacancies are formed from 1130°C to 1050°C during crystal growth [9] when v/G is larger than a critical v/G*COP. Nuclei of OISF, which are tiny oxygen precipitates [10], are formed from 1050°C to 850°C [11] at v/G between critical v/G*OISF and v/G*COP. Agglomerates of self-interstitials are formed around 1000°C [6] at v/G smaller than a critical v/G*L/D, where L/D refers to large dislocations. The dislocation is an agglomerate of self-interstitials. There is a region where no agglomerates of point defects are formed at v/G between critical v/G*L/D and v/G*OISF, and this is the condition that produces pure silicon. This region is divided into two portions, the self-interstitial rich region, PI, between critical v/G*L/D and v/G*I/V, and the vacancy rich region, PV, between critical v/G*I/V and v/G*OISF. As shown later, the behavior of oxygen precipitates during post-annealing processes employed in the fabrication of devices is quite different in the wafers taken from PI and PV regions.

For the production of pure silicon, it is important that v/G is kept between critical v/G*L/D and v/G*OISF over both the length and the radius of the crystal during its growth. It is difficult to keep v/G between the critical values of v/G*L/D and v/G*OISF across the entire radius using conventional techniques because G at the periphery of crystal is much higher than G at the center. The optimization of the hot zone and adjustment of the growing conditions makes G at the periphery and at the center much closer in value.

Figure 2 shows the axial distribution of defects in a crystal made with the growth rate ramping down and up under a condition by which pure silicon can be produced. The defects were determined by the measurement of recombination lifetime after the wafers were subjected to a two-step anneal, 800°C for 4 hr followed by 1000°C for 16 hr. The growth rate was changed during the course of growing the crystal, so v/G was varied along the crystal length in order to investigate the effects of v/G on the formation of grown-in defects in this condition. There is a region free of any agglomerates of intrinsic point defects between critical v/G*L/D and v/G*OISF, as shown in Fig. 2. Thus, setting the condition along the crystal length in the above manner produces pure silicon.

Particles and contamination in pure silicon
Figure 3 compares particle maps taken on wafers for >0.065µm particles from conventional CZ and from pure silicon processes. The particles were measured with KLA-Tencor's SP1-TBI, and atomic force microscope (AFM) images were taken on SPA 465 and SPA 360 systems. Figure 3a shows about 2000 particles on the conventional CZ wafer, and almost all of these particles are COPs, as indicated by AFM images. The pure silicon wafer shows only 21 particles of the same size (Fig. 3b), and AFM images confirmed that these were real particles or some defects formed during the wafer process, but COPs were not found in these wafers.

The number of particles larger than 0.106µm on conventional CZ and pure silicon wafers, as measured by ADE-CR in the mass-production line is shown in Fig. 4. The average number of particles on 10,000 conventional CZ wafers was 111.3, and on 50,000 pure silicon wafers, it was 12.6. This clearly indicates that using pure silicon crystals can dramatically decrease the number of particles.

Gate oxide integrity and other electrical characteristics of devices made on a pure silicon wafer are as good as or better than those fabricated on epitaxial or hydrogen-annealed wafers [12].

It may be interesting to note that the epitaxial wafers contain stacking faults. Also, Fe contamination two orders of magnitude higher than on polished wafers is found at the edges of hydrogen-annealed wafers. The device yield [13] is affected by both stacking faults and Fe contamination.

The radial distribution of bulk micro defects (BMDs) in different types of pure silicon wafers is shown in Fig. 5. The measurement of BMD density was performed after a two-step anneal (800°C for 4 hr plus 1000°C for 16 hr) by optical microscopy on a cleaved surface. The cleaved surface underwent Secco etching. As shown in this figure, PV regions exist at the center and periphery, and PI regions exist at intermediate radii. Because oxygen precipitate nuclei that are formed during crystal growth strongly depend on the concentration of vacancies just before the start of the formation, the density of BMD in the PI region was smaller than in the PV region.

Processes such as pre-annealing and polysilicon back coating (PBC) affect the BMD density in pure silicon. The effects of these processes on BMDs in the PI region were investigated. The annealing condition of PBC was the same as the pre-annealing condition of 665°C for 210 min. Using these conditions, the density of BMDs in the PI regions of pure silicon wafers was two to three orders of magnitude higher (Fig. 5). These results indicate that oxygen precipitate nuclei are formed even in PI regions during crystal growth. They grow during pre-annealing and become larger and stable at 800°C.

Gettering ability
Figure 6 shows the radial distribution of Fe concentration on pure silicon wafers subjected to various treatments. Fe concentration on the wafers was measured by deep level transition spectroscopy (DLTS) after intentional contamination by Fe of the order of 1x1012cm-2 using the spin-coat technique followed by annealing that simulated CMOS processing. This was done in order to investigate gettering ability of various pure silicon wafers [14]. Fe concentrations on pre-annealed pure silicon and PBC pure silicon, each subjected to a two-step heat treatment, are almost uniform in radial distribution, and they are about one order of magnitude lower than pure silicon. The results indicate that pure silicon subjected to intrinsic gettering (IG) or intrinsic plus extrinsic gettering (EG) types of treatment has good gettering ability even in the PI region, which is located about halfway along the radius. No BMDs were detected in pure silicon or pre-annealed pure silicon by optical microscopy after Secco etching. However, a small oxygen precipitate density on the order of 108-109cm-3 was detected by TEM observation everywhere except for the PI region in pure silicon. The results indicate that pre-annealing at a lower temperature (such as 660°C) can improve the gettering ability of PI in pure silicon.

Conclusion
We have described a CZ silicon crystal growth technology that produces single crystals without grown-in defects such as COP, OISF nuclei, and dislocations. Compared to other COP-free silicon such as epitaxial and hydrogen-annealed wafers, the production cost of these pure silicon wafers is lower, but the quality is equivalent or better. The technology of pure silicon has been applied to the production of 150mm, 200mm, and 300mm wafers. Pure silicon wafers have had better device yield compared to conventional CZ wafers in various device applications.

Acknowledgments
We would like to thank K. Ikezawa, Y. Suzuki, and our colleagues in the crystal production technology department for the preparation of pure silicon crystals. We would also like to thank Dinesh Gupta of Mitsubishi Silicon America for helpful technical discussions, and H. Koya, M. Koizumi, Y. Muroi, and K. Kurita for the evaluation of samples and preparation of figures.

References

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Hisashi Furuya received his BS, MS, and PhD in industrial chemical engineering from Tokyo Metropolitan University in 1978, 1980, and 1983, respectively. He is the manager of Mitsubishi Materials Silicon and has worked in the field of CZ single- crystal silicon for about 17 years. Mitsubishi Materials Silicon Corp., 4-3146-12 Hachimanpara, Yonezawa, Yamagata 992-1128, Japan; ph 81/238-28-3136, fax 81/238-28-3138, email [email protected].

Kazuhiro Harada received his BS and MS in metallurgical engineering from Touhoku University in 1986 and 1988, respectively. He is the assistant manager of Mitsubishi Materials Silicon and has worked in the field of CZ single-crystal silicon for about 12 years.

Jea-Gun Park received his MEng in 1988 at Hanyang University in Seoul. In 1994, he received his PhD at North Carolina State University. From 1985 to 1999, he worked on the development of high-performance wafers for dynamic access memory devices at Samsung Electronics Co. Since 1999, he has been a professor at the Graduate School of Industry at Hanyang University.