Issue



Low-temperature annealing system for 300mm thermal processing


06/01/2001







Woo Sik Yoo, Taro Yamazaki, WaferMasters Inc., San Jose, California
Toshiyuki Uchino, Trecenti Technologies Inc., Hitachinaka, Japan

overview
A production-worthy, five-wafer annealing system using six stacked hotplates is proposed for low-temperature (100-450°C) applications such as Cu, Al, SOG, photoresist, and low-k dielectric annealing for 300mm wafers. Thermal properties of the annealing system and wafer temperature profiles during annealing are characterized as a function of hotplate temperature and annealing time under various gas ambients. SOG process results are discussed. The productivity of the annealing system is evaluated as a function of annealing time.

Traditionally, low-temperature processing has been done either in a conventional large batch furnace (150-200 wafers/batch) or on a hotplate. The conventional batch furnace provides a reasonable throughput only for large batch processing. The hotplate system can process one wafer at a time and provides high lot size flexibility, but the throughput of a single wafer hotplate system is inversely proportional to the process time. As device designs advance, the thermal budget becomes tighter and new materials are frequently introduced. Many of the new materials, such as Cu and low-k dielectrics, need low-temperature processing.

To shorten the process development cycle, the development of a low-temperature annealing system with improved lot size flexibility is strongly desired. In fact, this flexibility is one of the important system selection criteria for 300mm wafer fabs. Single-wafer processing is preferred from the viewpoint of process quality control and production scheduling. The need for a production-worthy, low-cost, low-temperature annealing system with lot size flexibility and high energy efficiency is growing rapidly as wafer size increases.


Figure 1. Schematic diagram of a 300mm Si wafer between stacked hotplates.
Click here to enlarge image

With new equipment design concepts and optimized processes for single-wafer processing, current single-wafer equipment has productivity and process capability equivalent to batch systems. Currently, some critical annealing is performed by single-wafer rapid thermal processing (RTP) equipment. We presently see more and more RTP steps being used for the smaller device nodes and for almost all 300mm wafers. One critical process parameter to enable single-wafer RTP is the process time itself. Often, the optimized process time is 1-2 minutes, but there are other thermal processes for which single-wafer processing is too slow. The low-temperature annealing system discussed in this article retains the advantage of batch furnaces by processing multiple wafers simultaneously, while maintaining process flexibility with small wafer lot sizes.

The lower thermal budget and the flexibility of single-wafer processing systems makes RTP more attractive than conventional batch furnaces in many thermal processing applications above 600°C. Most RTP systems employ lamps for wafer heating and optical pyrometry for wafer temperature measurement and control. However, accurate and reliable wafer temperature measurement and control below 600°C using optical pyrometry is still a very challenging task [1, 2] because the lamp-heated RTP systems use optical interaction between lamps and a silicon wafer. Variation in doping level, reflective layers, and patterns on the wafer can all have a negative influence on accurate wafer-temperature measurement and control, especially below 600°C. Moreover, highly reflective layers such as Cu films reflect more than 90% of light from lamps and make wafer heating difficult [3]. This can shorten the lifetime of the lamps. To reduce these problems in lamp-heated RTP systems, an indirect wafer heating method is proposed for annealing wafers with highly reflective films [3]. As wafer size increases, large-batch processing becomes impractical. A significant increase in thermal mass results in the increase of temperature ramp-up and ramp-down times. This loading effect cannot be avoided as long as batch systems are used. To overcome the difficulty in temperature measurement and control in RTP systems and the constraints in lot size and throughput of conventional furnaces, new systems need to be developed for low-temperature annealing applications for 300mm wafers.

In this article, a resistively heated, hotplate-based annealing system is proposed for low-temperature (100-450°C) applications such as annealing of Cu, Al, spin-on-glass (SOG), photoresist, and low-k dielectrics. The design concept of the annealing system is described in detail. Wafer temperature profiles during low-temperature annealing in the system are characterized. SOG process results using the system are discussed. The productivity of the system is evaluated as a function of annealing time.

System configuration
For higher energy efficiency as well as temperature uniformity, repeatability, and stability, resistively heated hotplates were used as heat sources to heat 300mm Si wafers in this study. Figure 1 shows a side view and top view of stacked hotplates with a 300mm Si wafer. The hotplate is made of aluminum and has an embedded heater. The diameter and thickness of the hotplate are 400mm and 30mm, respectively. There are three standoffs to keep the distance between a wafer and the hotplate constant. The standoffs are equally spaced on the perimeter of a 210mm diameter circle. This stacked hotplate configuration was used as a heat source for wafer annealing. A loading effect, which is normally observed in conventional batch processing systems, can be eliminated by using stacked hotplates as a heat source.

Individual wafers will be surrounded by massive hotplates. In the standard system configuration, six hotplates are stacked to process five 300mm wafers simultaneously.


Figure 2. Temperature dependence of thermal conductivity of Al, Si, and air.
Click here to enlarge image

In the operating temperature range of 100-450°C, conduction and convection are the predominant heat transfer mechanisms from the hotplates to a wafer. A shorter distance between hotplates provides better heat transfer to a wafer, but the tolerance in wafer handling height becomes tighter. For this reason, the distance between the hotplates was kept at 20mm in this study. During annealing, the wafer is placed on three standoffs. The wafer is placed approximately in the middle of the two nearest hotplates. No moving parts are used in the process area. Wafer temperature profiles on hotplates were investigated as a function of the hotplate temperature and process atmosphere.


Figure 3. Wafer temperature ramp rate at different hotplate temperatures under He and air environments.
Click here to enlarge image

Temperature uniformity of individual hotplates was characterized using infrared thermography in the temperature range of 100-450°C. The symmetric geometry of the hotplates helps maintain temperature uniformity. The temperature variation across the hotplate is within ±1°C at 400°C. The temperature uniformity on individual hotplates results from the high thermal conductivity of aluminum and their relatively large thickness (30mm). The thermal conductivity of aluminum is almost twice that of silicon at room temperature. As temperature increases, the thermal conductivity ratio of Al to Si becomes larger and approaches 4 at 600K. The temperature dependence of the thermal conductivities of Al, Si, and air is shown in Fig. 2 [4].

Wafer temperature profile
300mm bare Si wafers with instrumentation thermocouples were annealed in the low-temperature annealing system at different temperatures under one atmosphere of air. The temperatures of the top and bottom hotplates were controlled separately, but the temperature setpoints of both hotplates were kept the same. Temperature profiles of a wafer in stacked hotplates were measured at hotplate temperature setpoints of 200, 250, 300 and 350°C. The wafer-handling sequence during the wafer temperature measurement is as follows:

  1. The wafer-handling robot picks up a wafer.
  2. The robot enters the wafer between hotplates in the process area.
  3. The robot places the wafer onto standoffs.
  4. The robot leaves the process area.
  5. The wafer stays between hotplates in the process area for a given process time.
  6. The robot goes into the process area.
  7. The robot picks up the annealed wafer.
  8. The robot removes the wafer from the process area at process temperature.
  9. The robot places the processed wafer into the cooling station.

Figure 3 shows wafer temperature ramp-up and ramp-down profiles in the system. As soon as the wafer is inserted between the stacked hotplates, the wafer temperature initially increases almost linearly and then it saturates at slightly below the hotplate temperatures. When the wafer is annealed in a high thermal conductivity gas ambient such as He or H2, the wafer temperature ramp-up and ramp-down rates are higher than those in air.

The saturated wafer temperature is also higher in He or H2 gas ambient compared to air. The wafer temperature profiles suggest that a noncontact thermal annealing method is gentle and ideal for low-temperature annealing applications [5]. Multipoint wafer-temperature measurements showed a very good within-wafer temperature uniformity.

System configurations and productivity
The low-temperature annealing systems are configured two ways. Figures 4a and 4b show the schematic diagrams. In one configuration, the stacked hotplates are exposed to the atmospheric air environment. This configuration keeps the system simple in structure and provides high productivity. The atmospheric system consists of two FOUP openers, an atmospheric wafer-handling robot, six hotplates, and five cooling stations. Applications such as SOG anneal and photoresist bake can be done in this type of system. Simultaneous five-wafer processing is done in the system without the loading effect. The productivity of the system is not affected very much by annealing times up to five minutes because of the five-wafer simultaneous processing.


Figure 4. Schematic diagrams of low-temperature a) atmospheric and b) airtight annealing systems.
Click here to enlarge image

The other configuration is designed for applications that have to be done in an oxygen-free ambient. In the airtight (oxygen-free) system, an aluminum enclosure surrounds a loadlock (which also serves as the cooling station), a transport module (including a vacuum wafer-handling robot), and the stacked hotplates. The system also has two FOUP openers and an atmospheric wafer-handling robot. This system is designed for low-temperature annealing processes in a controlled gas environment, such as a H2 mixture environment. To maximize productivity and process gas efficiency, 25 wafers are loaded into the loadlock prior to the process start. This configuration also allows five-wafer simultaneous processing.


Figure 5. Throughput of atmospheric system as a function of process time.
Click here to enlarge image

Figure 5 shows the throughput as a function of annealing time in the atmospheric annealing system and the airtight annealing system. For 1-3 min annealing processes, the wafer handling is the limiting factor and the throughput is ~60 wph. For annealing processes >4 min, the annealing time is the limiting factor for throughput. Because of the five-wafer simultaneous processing capability and gentle wafer temperature ramp-up characteristics of the system, we are able to achieve very repeatable process results at higher productivity compared to conventional single hotplates and batch furnaces. Lot size flexibility is also improved compared to the batch furnaces, without reducing productivity. Typical throughput of the airtight annealing system is about 20wph for a 5-min process. Power consumption of both the atmospheric and the airtight annealing systems is 3-7kW at a maximum process temperature of 450°C.

SOG annealing and other applications
SOG involves spin coating and annealing (baking and curing). Several low-temperature (up to 400°C) thermal treatments are necessary to ensure that the desired thickness and physical properties are obtained and the solvents are removed from the SOG. Control of the thermal treatment of SOG films is very important for SOG processing in general. Insufficient curing will cause moisture and solvent outgassing through the vias during the subsequent metal deposition.


Figure 6. a) b) Average thickness shrinkage and c) d) refractive index as a function of annealing temperature and time.
Click here to enlarge image

During the SOG baking and curing process, the solvents and water outgas from the film. This causes considerable volume shrinkage in the SOG and creates a high tensile stress in the film. This stress could cause cracking in the SOG. Improper baking, or curing too quickly, could cause the upper layers of the SOG to be completely polymerized and prevent adequate moisture and/or solvent evaporation from the bulk of the SOG. Outgassing can cause trapping of hot and volatile compounds under a cap of fully polymerized SOG at the upper layer of the SOG. These trapped volatile compounds may also then contribute to cracking and popping [6-8]. To provide sufficient time for outgassing of the solvents and moisture, the baking and curing must be performed without causing any thermal shock [6]. A gradual increase in temperature is considered to be ideal for the baking and curing cycle. The SOG is typically baked on hotplates and cured in batch furnaces. Thermal shock during the hotplate baking makes process control difficult. Gradual heating in a single-wafer annealing system is not practical for productivity. A long process cycle and large batch size processing pose queuing problems for small production lots. Large batch processing in a furnace often causes particle problems because of the high concentration of solvents and water vapor released from SOG films.

Spin-coated organic SOG films on 200mm wafers were baked in the five-wafer atmospheric annealing system under 1 atm air. An average as-spun thickness and refractive index of SOG films were 360nm and 1.428, respectively. The annealing temperature was varied in the range 200-400°C. The annealing time was also varied from 1-5 min. The annealing temperature and time referred to in this paper are the hotplate temperature and the wafer residence time (from wafer-in to wafer-out) between the stacked hotplates. The film thickness shrinkage and refractive index changes after annealing under different conditions are shown in Figs. 6a-6d.

As annealing temperature and time increase, thickness shrinks more due to the loss of solvents and water from the SOG film (Fig. 6a). Thickness shrinkage was controlled between 3% and 20% by adjusting the annealing temperature and time (Fig. 6b). The target thickness of SOG films after annealing is 300nm. The thickness shrinkage of 17-20% and refractive index of 1.420 are desired for preventing cracking during annealing (baking) and obtaining desirable selectivity of etch rate in the following etch back process step. The refractive index of films also decreases as the annealing temperature and time increase (Figs. 6c and 6d).

The refractive index and average thickness shrinkage of SOG films were measured before and after annealing. The refractive index of SOG films shows very strong correlation with the average thickness shrinkage of SOG films regardless of the annealing temperature and time. The refractive index decreases as the SOG film shrinks. It decreases gradually up to 18% thickness shrinkage and drops abruptly beyond 18% thickness shrinkage. The average thickness uniformity of SOG films after annealing is 0.5-1.5% (1s). The desired thickness of 300nm (equivalent to thickness shrinkage of 17-20%) and refractive index of 1.420 can be obtained by selecting the appropriate annealing temperature and time. It is possible to control SOG film shrinkage and properties using the atmospheric annealing system in the wide range of process conditions [9].

The repeatability in thickness shrinkage, refractive index, and etch rate selectivity of SOG films after annealing was investigated using device production wafers. Split device yield tests were performed comparing conventional batch furnace, conventional contact-type hotplate, and the atmospheric low-temperature annealing system. The atmospheric low-temperature annealing system provided the highest device yield. Other systems (hotplate and furnace) generate many particles during the process over time and require frequent maintenance for cleaning. This interrupts the device manufacturing process and can cause device yield problems. Device test results on 200mm production wafers indicate good reliability and repeatability of the SOG annealing process in the atmospheric annealing system.

Conclusion
A production-worthy, five-wafer annealing oven using six stacked hot-plates was proposed for low-temperature (100-450°C) annealing applications for 300mm wafers. Thermal properties of the annealing system were characterized as a function of hotplate temperature and annealing time under various gas ambients. Two types of system configuration were introduced. The productivity of the annealing system was evaluated as a function of annealing time. SOG films were annealed in the stacked annealing oven under various annealing conditions, and the changes in physical properties were characterized. The amount of film shrinkage and the refractive index of SOG films were controlled by selecting annealing conditions.

The productivity and lot size flexibility in the five-wafer atmospheric annealing system were significantly improved compared to conventional SOG annealing methods using hotplates or batch furnaces. The low-temperature annealing system is promising for low-temperature annealing of Cu, Al, photoresist, and low-k dielectrics.

Acknowledgments
The authors wish to thank Mr. T. Fukada, Mr. Y. Hiraga, Mr. K. Kang, Ms. J. Lau, and Mr. S. Fujimoto of WaferMasters, Inc. for their dedication to this project. The authors also wish to thank Mr. K. Watanabe and Mr. A. Koike of Trecenti Technologies for their helpful discussions and encouragement during this work.

References

  1. I. Jonak-Auer, "RTP Temperature Calibration Using Titanium Silicides," Solid State Technology, Vol. 43, No. 2, p. 69, Feb. 2000.
  2. K. Maex, "Proc. Advances in Rapid Thermal and Integrated Processing," NATO ASI series E218, ed. F. Roozeboom, Chap. 12, 1996.
  3. Y.Z. Hu, R. Sharangpani, S.P. Tay, "Kinetic Study of In-Situ Copper Oxidation and Reduction using Rapid Thermal Processing and Its Application in ULSI," Electrochemical Society Proceedings, Vol. 2000-9, p. 329, 2000.
  4. CRC Handbook of Chemistry and Physics, 75th Ed, ed. D.R. Lide, CRC Press, Chap. 6 and Chap. 12, 1994.
  5. W.S. Yoo, T. Fukada, "Wafer Temperature Characterization during Low Temperature Annealing," Electrochemical Society Proceedings, Vol. 2000-9, p. 355, 2000.
  6. G.K. Rao, Multilevel Interconnect Technology, McGraw-Hill, New York, Chapter 2, 1993.
  7. C.Y. Chang, S.M. Sze, ULSI Technology, McGraw-Hill, New York, Chapter 8, 1996.
  8. R.F. Cook, E.G. Liniger, "Stress-Corrosion Cracking of Low-Dielectric-Constant Spin-On-Glass Thin Films," Journal of Electrochemical Society, Vol. 146, p. 4439, 1999.
  9. W.S. Yoo, T. Fukada, J. Yamamoto, "SOG Annealing Keeps Its Cool," European Semiconductor, 17, August 2000.

Woo Sik Yoo is the chief technical officer and a co-founder of WaferMasters Inc. He received his BS degree in electronic engineering from Dongguk University in Korea, his MS and PhD degrees in electrical engineering from Kyoto University, and his MBA degree from Western Connecticut State University. He has served as a research and process engineer at ATMI, Novellus Systems, and Lam Research, followed by positions as senior product technologist and product marketing manager at Mattson Technology. Yoo has written more than 80 papers on RTP, dielectric PECVD, and wide band-gap compound semiconductors. WaferMasters Inc., 246 East Gish Road, San Jose, CA 95112; ph 408/451-0856, fax 408/451-9729, email [email protected].

Taro Yamazaki is the president and CEO of WaferMasters Inc. and one of its co-founders. He received his BS degree in mechanical engineering from the Ashikaga Institute of Technology in Japan. He has more than 20 years of international business experience in the semiconductor industry. Yamazaki has served as director of market development for Mattson Technology and general manager of the export department for Marubeni International Electronics.

Toshiyuki Uchino is senior manager of the manufacturing technology department of Trecenti Technologies Inc. He received his BS degree in mechanical engineering from the University of Tokyo and his MS degree in manufacturing systems engineering from the University of Wisconsin-Madison. Uchino worked at Hitachi for 15 years as an equipment engineer for thermal processes, and he contributed to the development of the vertical diffusion furnace.