We need better communications behind subwavelength mask manufacturing
06/01/2001
J. Tracy Weed, Numerical Technologies
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As the semiconductor industry moves to the 130nm process node and beyond, photomask manufacturing has fundamentally changed. Technologies such as phase shift masks (PSMs) and optical proximity correction (OPC) have become part of the standard lithography process and the photomask is moving from a commodity product to a value-added part of lithography. Yet, despite the changing role of the photomask in the chipmaking process, there has not been, to date, a substantial change in the methods of communication between chipmakers and maskmakers. This lack of communication stands as a significant limitation in advanced chip production.
Semiconductor manufacturers usually set photomask specifications with the best of intentions. They take internal data or modified industry data (e.g., from the International Technology Roadmap for Semiconductors) and apply it to areas such as linearity, defects, CDs, and uniformity, with the hope that these photomasks can be used to provide the desired level of device performance. In many cases, however, these photomask specifications will take you through a long and torturous path to get you where you want to go. They may be too tight or too loose and may not match your outcome. Yet, photomasks are inspected, accepted, or rejected based upon these specifications on a daily basis.
To further complicate matters, in a subwavelength-manufacturing environment, the nonlinear nature of chip-manufacturing processes poses a difficult challenge for setting accurate specifications. Specifications must consider new materials, smaller dimensions, and effects, such as pitch dependency, that are just now beginning to be understood. In this environment, overset specifications can drive critical plates to be rewritten 10-15 times. While the impact of this is obvious and in some cases unavoidable, the same photomask with the right specifications can rocket out of the mask house into the revenue-hungry process line of the chipmaker in significantly less time with a significantly reduced cost.
Inappropriate specifications simply increase the overall manufacturing cost of the device without providing any long-term performance benefits. Worse, because they increase the complexities of mask manufacturing, they can have a direct negative impact on the availability and turnaround time of the mask. In the semiconductor industry, being the second to market can result in lower average selling prices and missed design wins.
There are three steps the industry can take to improve the process of specification generation and create a win-win situation for all those involved.
First, groups must work together to set realistic specifications. This is often easier said than done. Fab engineers need to recognize that the maskmaking industry possesses considerable talent and expertise that can and should be leveraged in determining optimal specs for advanced mask applications.
Mask manufacturers like Dai Nippon Printing, Toppan, Photronics, and DuPont Photomask are all helping to drive the mask technology that the broader semiconductor community requires for success. Dai Nippon Printing, for example, has been delivering defect-free advanced alternating aperture PSMs for the better part of a year. Photronics has worked closely with MIT's Lincoln Labs in its recently announced efforts to successfully produce transistor gates as small as 9nm. DuPont has key customer engineers working side by side with mask house engineers to ensure the delivery of advanced photomasks in its Advanced Reticle Center. By working together more closely, fab and mask engineers can marshal a higher level of expertise than either can attain separately, and can apply that to the task at hand.
Second, the industry must realize that a completely "defect-free" photomask is unrealistic at this time.
With the difficulty, expense, and time required to repair advanced photomasks, fabs must actively embrace technology solutions, where appropriate, that are "good enough." There are increasing examples of fabs exploiting the capability of their internal mask houses to provide solutions that are "good enough" to achieve the desired device performance and meet aggressive turnaround time requirements.
Finally, chipmakers and maskmakers must adopt common solutions that allow them to effectively deal with what "good enough" means. This can include developing simple, reality-based fabrication techniques that attempt to minimize complexity, and utilizing advanced simulation technology to quantify "good enough" before the photomask leaves the production floor. It can also include continuing to support the development of advanced inspection and repair technology, since the need to know what is on your reticle so that the killer defects can be addressed will never go away.
Subwavelength manufacturing utilizing PSM and OPC makes it difficult to determine easily and accurately just what "good enough" is. The design layout does not have a one-to-one correspondence with what appears on the mask, and what appears on the mask does not have a one-to-one correspondence with what prints onto the wafer.
The traditional approach has been to make subjective assessments on defect printability and to then run wafer results on each mask to resolve printability issues. This manual approach is time-consuming, cost-prohibitive, and inconsistent.
What both mask and IC manufacturers require is a web-based, automated simulation tool that will enable the analysis of mask printability, based on what would actually appear on the wafer, to distinguish "nuisance" from "killer" defects on the mask. Such a tool would enable the mask manufacturer to conduct advanced defect printability analysis on the mask before shipping and would also enable the fab to more effectively perform incoming mask qualification, as well as through-repair and post-repair verification. This approach offers the additional benefit of providing common mask defect data to both mask and fab engineers, thereby facilitating communication between the two groups.
Semiconductor manufacturing is continuing to increase in complexity with each generation. While great strides have been made to build the infrastructure needed to cope with manufacturing challenges created by this complexity, more remains to be done.
Gone are the days when a fab could build its own masks and process equipment. So, to continue moving the industry forward in the subwavelength environment, all of the key players in the design-to-silicon chain must work closely together to build the tools and establish the communication methodologies needed to reduce manufacturing costs, while continuing to deliver the advanced ICs required for leading-edge electronics applications.
J. Tracy Weed is senior director of marketing and business development at Numerical Technologies, 70 W. Plumeria Dr., San Jose, CA 95134-2134; ph 408/919-1910, fax 408/919-1920, e-mail [email protected].