Industry's problems, solutions exposed at lithography's annual showcase
05/01/2001
What's ahead for litho?
Even though lithography has been "the whipping boy of the industry for so long," there will be greater problems as the industry approaches the wall of CMOS technology, said Dennis Buss, VP of silicon technology development at Texas Instruments, Dallas, TX, to the attendees of SPIE's 26th International Symposium on Microlithography.
While it seems as if the major industry challenges are lithographic, Buss noted that some underlying problems don't get as much notoriety. There will need to be "tremendous breakthroughs just to get to the wall on the industry roadmap." The industry's drive is now system-on-a-chip (SOC) integration, Buss said, replacing microcomputers and memory for PCs.
"Consider that the cell phone still has something like 250 components. We are going to see the drive to integrate all these functions, putting everything eventually on one chip," he said. "This integration will take place in several distinct steps, perhaps seeing the single chip by 2005.
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Nikon: full speed ahead
The IBM PREVAIL e-beam column for e-beam projection lithography is now at Nikon in Japan, where this technology is being prepped to emerge commercially as the Nikon EB-stepper. Although Nikon officials had targeted production tools by 2004, they are now accelerating the program.
"For SOC, transistor scaling will continue to be important technology, but it is not the sole driver. We have to look at things like gate length limitations, thinning gate insulator problems, and associated leakage currents," Buss added.
Buss sees IC technology getting to the point where "devices start working less and less like switches. While it is common to think that the industry is based on silicon, it is really based on silicon dioxide. Within this view, in five years, we are going to have to abandon silicon dioxide and that is the major problem that puts lithography in perspective."
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We are looking at the industry of the future, but so far the [culminating] invention that will carry it has not been made. - Denis Buss, VP of silicon technology development, Texas Instruments
Looking at the emerging lithography generations, Buss outlined for SPIE attendees that a natural, but difficult lithography process k1 limit of 0.25 dictates a limit of 70nm for 193nm lithography, 50nm for 157nm lithography, and "34nm is where NGL is really needed, based on this plan. But the limits associated with the fundamentals of CMOS are going to cause 'disruptions' even if we could get to 20nm with lithography," he summarized.
Both Buss and Karen Brown, deputy director at NIST, Washington, DC, addressed the IC industry's pending wall at the limits of CMOS technology. Brown's message was that while lithographers need to continue their work at making lithography cost effective for the near term, in the not-too-distant future "disruptive technologies" are going to change the industry as we know it. "Make no mistake," said Brown, "for the short term, the real challenge is manufacturable solutions for each technology element [in the industry roadmap]; these are needed or there will be a crisis."
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The needed disruptions will come from a range of research possibilities that include molecular electronics, that is, "moletronics" - where molecules perform electronic functions - or perhaps quantum switches. - Karen Brown, deputy director, NIST
Brown described disruptive technologies as changes in the industry similar to the invention of the transistor in 1947, which disrupted vacuum tube technology, and the invention of the IC in 1958, which disrupted the limitations of copper wiring.
"Longer term," Brown noted, "there is evidence that lithography cost per wafer at the 100nm node may exceed the affordable total process cost per wafer." Brown sees the industry headed away from its classic characteristic of "flat wafer processing costs independent of the ground rules." She outlined the explosion occurring in mask costs as an example; the industry is on a path where "masks alone could exceed the affordable cost for all of lithography," said Brown. "And masks are not alone," she added, showing charts with exposure tools accelerating toward eventual $25 million/system and wafer fabs themselves headed toward $50 billion out beyond 2010.
"There is something wrong with cost equations and we need some breakthroughs [to totally new IC technologies] to do something about it." The relief for lithographers, not necessarily the industry, is that Brown foresees that "the roadmap is destined to end around 2010, perhaps, because of physical and economic limits." This is where she sees the emergence of disruptive technologies.
Brown told attendees that the needed disruptions will come from a range of research possibilities that include molecular electronics (i.e., "moletronics" where molecules perform electronic functions) or perhaps quantum switches.
She said, "Moletronics makes a lot of sense because even the biggest molecule is very small [compared to current microelectronics] and fabrication is easy [compared to today's methods] because it uses organic synthesis, thus eliminating the need for wafer fabs as we know them today." Even though this work is still at the university and laboratory level, Brown finds much of the reported work very encouraging. For example, she cited HP work with molecular electronics that has resulted in self-assembled parallel wire technology.
"Even though self assembly removes the need for lithography, moletronics is not without its own 'grand challenges,'" noted Brown, "including metrology, defect detection, and evaluation, and simulation to correlate structure and function." Such areas are being pursued by NIST researchers and others.
"While also a possibility, quantum computing (which uses up and down atomic spin for electronic function) is more speculative and may not be scalable to large computing applications," said Brown.
Brown closed by saying, "Beyond the [CMOS] wall in the current industry roadmap, there are a lot of new opportunities and challenges. It will be interesting to see how this [SPIE Microlithography] meeting will evolve over the next ten years. The work that has to be done will increasingly require multidisciplined teams, integrated teams of engineers that today don't even speak the same [technical] language."
As for which disruptions will work, it is Buss' view that today we are where the industry was when TI's Jack Kilby invented the IC in 1958, tying together all the fundamentals about electron states that had been put together since the 1930s. "Beyond CMOS, there is a great abyss. There are a lot of ideas, like molecular electronics. The fundamentals of molecular electronics are being done, but no one has come up with the way to make it into ICs. The thing that is missing is the 'Jack Kilby [caliber] invention for the future.' We are looking at the industry of the future, but so far the [culminating] invention that will carry it has not been made."
Stepping through SPIE conferences
Over 3000 attended the 2001 SPIE Microlithography Symposium ending March 2, "roughly 25% more than last year," said symposium chair Michael Postek from NIST. This year's symposium endeavored to break down the barriers between resist, metrology, optical, and emerging technologies with ambassadors from one conference speaking in others and special joint sessions on cross-cutting issues. The result was a unique feeling of common purpose: helping the semiconductor industry to the next technology node.
Metrology conference
One focus within metrology is the need to move from assuring "compliance" with specifications to a real-time process "control" to deal with the challenges of low k1 lithography. Metrology conference keynote speaker Christopher P. Ausschnitt of IBM described how familiar optical techniques can be upgraded to such a role by placing special metrology targets on product wafers, measuring in-line, and using the information to control focus, overlay, and dose. According to Ausschnitt, modeling to interpret data in terms of the process window must become an integral part of the metrology function. "The alternative is faith-based lithography," quipped Auschnitt.
Optical lithography experimenter Mike Fritze of MIT described the power and challenges of extreme low k1 lithography to the metrology conference. His message was that while phase-shifting mask (PSM) techniques can produce resist lines down to 40nm, the resist rounding at the tops of the lines confounds current SEM metrology algorithms. Metrologists must learn to measure these small features accurately across the exposure field and wafer in order to identify failure modes.
Optical lithography
In a related talk in the optical lithography session, Fritze reported 9nm gates (complete with a cobalt silicide spot at the top) patterned using a 248nm three-exposure, two-resist "gratings of regular arrays for ULSI lithography" process, dubbed GRATEFUL (Fig. 1). The use of dense phase gratings was also endorsed by Albert Wong, a professor from the University of Hong Kong, as an aberration-reducing tactic. Chien-Ming Wang described the work of a team from UMC (Hsinchu, Taiwan) and Numerical Technologies to implement strong PSM to produce chips with 80nm gates. While line-end shortening has still not been completely conquered, the 248nm PSM technology seems superior to exposing at 193nm and NA >0.70, according to Wang. However, Carla Nelson Thomas of Motorola reported that they were already in pilot production of 75nm CD chips with 18nm 3s variation using a related complementary-PSM method.
Resist and processing
Speaking as an ambassador from the optical lithography session, Tim Brunner of IBM petitioned resist makers to develop negative tone resists as good as their recent excellent positive tone products. According to Brunner, certain features, such as lines >175nm at 400nm pitch, are more readily patterned in negative tone resists, all things being equal. The improved process window is a result of the increased normalized log slope of the darker regions of the aerial image, but the inadequate performance of current resists can overcome intrinsic optical advantages.
Yoshiyuki Yokoyama of Hitachi described beefy new ArF negative resists with androsterone incorporated in the polymer backbone. Because the development rate of these materials changes due to intra-molecular esterification, rather than cross-linking, they swell less than current formulations, printing 100nm line-spaces and 80nm isolated lines. I-Hsiung Huang of UMC reported a clever negative-resist trick to pattern via-first damascene structures: since exposed negative resist does not mix with a second layer applied on top, it is possible to print via holes in one layer, coat, and print the trenches on the top layer. The entire two-resist-layer via-interconnect structure is then transferred into the low-k oxide in one etching step. This MURPAS (multi resist patterning stacks) system improves via-to-trench alignment and cost for 200nm trenches with 175nm vias, according to Huang.
Simulation and design
Other talks showcased recently matured rigorous electromagnetic field simulation software as a means to predict and interpret imaging phenomena. Andreas Erdman of the Fraunhofer Institute, Erlangen, Germany, described how such systems improve the accuracy of standard imaging algorithms and help disentangling aberration effects. Armin Semmler described simulations done by his team at Infineon, Munich, Germany, to understand the effects of different perturbations on images projected from different PSM structures. However, rigorous methods are still too slow for many purposes, including full 3D simulation of realistic chip structures. Konstantinos Adam of the University of California, Berkeley, received the "best student paper" award for his simplified edge transition model for the same phenomena.
Rigorous EMF simulation is now sophisticated enough to apply to complex multilayer EUV masks, and Christof Krautschik and a team from ASET, Atsugi, Japan, used that technique to predict Bossung curve effects in EUV exposure. Because EUV masks are illuminated on one side of the normal to the plate, 70nm-sized focal shifts arise that depend on feature orientation, pitch, and other parameters. The off-axis illumination also produces line shifts and asymmetries, which can be largely dialed-out in alignment at best focus. However, the underlying reason for these anomalies is the wandering of the complex amplitude reflected by different mask regions and structures. This wandering amplitude can fill the unit circle in the complex plane "and then some," according to Krautschick.
Simple analyses of DUV and EUV imaging assume that the amplitude is either 0 or ±1 at the mask plane, but it is not yet clear whether the extra complexity of the EUV situation has any consequences beyond those that have turned up in EMF simulations at longer wavelength.
Another common issue is the dearth of quanta at short wavelengths that leads to statistical fluctuations in exposure dose. According to Sean O'Brien and Mark Mason of Texas Instruments, Dallas, TX, a 20mJ/cm2 resist requires only 25,000 157nm photons to expose a 90nm contact hole. Intrinsic Poissonian fluctuations of the photon number will cause 0.13% of these holes to receive less than 98% of the nominal dose, and those holes will fail to open if the exposure latitude is 4%, as expected. Such a defect level is intolerable for today's 6s semiconductor manufacturing requirements, let alone meeting future 8 or 9s processing. The quantum exposure statistics situation will almost certainly be worse for 13nm EUV as the fractional fluctuations will be 3x worse at the same resist sensitivity, and probably worse still for electron projection lithography (although perhaps not for electron direct-write where the current can be controlled for each contact).
While lithographers have gotten used to images that differ a bit from the mask patterns that produced them (and metrologists are learning to cope), Alan E. Rosenbluth and a team from IBM have buried the concept of "what you see is what you get" once and for all. In the new scheme described by Rosenbluth, an optimization program is asked to create the mask and illumination distributions that maximize the exposure latitude (or process window volume) for a particular target aerial image, no holds barred. While current programs can deal only with simple targets, such as the storage nodes or isolation in a DRAM, the aerial images produced are markedly superior to those found by any other method. However, mask structures bear no apparent relationship at all to target patterns, often having half the apparent pitch. The corresponding optimized off-axis illumination erases unwanted phase steps, etc. from the image, approximating the target pattern. Neither the mask nor illumination aperture technology is especially demanding, although double exposures may be required to deal with the irregular DRAM peripheral circuits.
J. Fung Chen and co-authors from ASML Masktools, DuPont Photomasks, and Petersen Advanced Lithography have revived the concept of 100% transmission attenuated PSMs with optimized off-axis illumination for fine-line patterning with a single exposure. To overcome the strong optical proximity effect induced by this mask technology, the authors have implemented newspaper-style "halftoning" to fabricate non-printing assist features. Initial wafer results indicate that complex sub-100nm patterns can be printed with a 400nm DOF using 248nm off-axis illumination (Fig. 2).
New hardware
The traditional Friday sessions on new exposure tools focused on new platforms enabling high-throughput 300nm production. Boudewin Sluijk of ASML showed an animated video illustrating the operation of the two wafer stages of the ASML Twinscan system. While one wafer on one stage is being exposed, the other stage is performing an unload-load-alignment cycle. After exposure, the stages exchange locations and roles. Both wafer stages couple via linear motors to the same reaction mass, which performs a complex motion but allows a moving average error below 2.5nm. Bert Vleeming of ASML showed early resists results for its ArF /1100 large NA scanner. With annular illumination, the 0.75 NA system prints 100nm line-space patterns with an MSD <7nm (3s). The actinic wavelength reticle alignment system reduces single machine overlay to <11nm.
Kazunori Iwamoto of Canon warned about simple interpretations of MSD numbers. According to Iwamoto, it is the variation in the MSD that directly affects images and process windows. The proposed 6000-series Canon platform is designed to have MSD=5±2nm at 140 300mm wafers/hr. Tsuneo Kanda of Canon reported reducing the rms aberrations of its ULEX03s lens below 0.02 waves, sufficient to print 130nm with binary masks and 70nm lines with 150nm spaces using strong PSM.
Tomoyuki Matsuyama described the way in which Nikon reduced the glass volume of its 0.75NA 248nm lens by 40% using two aspheric surfaces. The total rms aberration of the last 5 lenses was below 0.021 waves.
Harry Sewell of SVGL proposed an adaptive optics solution to thermally and environmentally induced aberrations of a catadioptric system. He showed a scheme for using 24 actuators to bend the main mirror, which happens to be in the pupil plane in SVGL designs, according to inputs from aerial image sensors.
Panel discussions and joint sessions
At SPIE, the BACUS working group held its traditional panel discussion about reticle-related issues: theme "Reticle Defects - Will They Break Moore's Law?" The panel's general consensus that even 50nm defects, which will be printable in 2005, will not stop the industry. Greg Hughes of DuPont Photomasks summed up the industry's position when he said, "We will be able to repair all defects that we find and we can't be blamed for defects we cannot find."
The lithography technical group's panel discussing "157nm Lithography: What is needed to have it on time?" seemed less reassuring. Panelists could not agree when "on time" was. Will Conley of Motorola stated: "It will be ready when it was ready," and then listed many issues from MEEF to integration to outgassing, all yet to be resolved. Later speakers pointed out other challenges, such as shipping reticles without pellicles, CaF2 quality, and timing. Yan Borodofsky of Intel proclaimed that if 157nm at k1=0.4 isn't solid in 2002, the first generation of 70nm chips will be tailored to the capabilities of advanced 193nm tools. If the technology isn't production-worthy in 2004, Borodofsky claimed that it would miss the window of opportunity. Panelists from Nikon and Canon projected mass production of 157nm tools in 2005, too late according to Borodofsky's time-table.
A special panel discussion, "When will EUV tools be needed and available," produced even more disturbing conclusions. Paulo Gargini of Intel pointed out that the first opportunity to insert 193nm had been missed and that the key opportunity to insert EUV would come in 2003. However, Scott Hector of Motorola pointed out that the cost of having EUV ready for 70nm in 2005 would be ~20x the funds spent on 248nm lithography in 2000, roughly $10 billion [editor's estimate]. While there were technical challenges in the source and mask substrate, the panel did not expect any technical show stoppers. Hector, however, pointed out that a throughput of 80 wafers/hr will be needed to justify the projected tool cost, which falls on the familiar exponentially rising line. Such a throughput requires a 40-fold improvement beyond current technology.
Don Sweeney of Lawrence Livermore Laboratories reported that it currently takes a full year to make a mirror set for EUV. Industrial insertion would require manufacturing 300 such sets/year, a daunting challenge. However, the final word was perhaps Paulo Gargini's who pointed out that 13nm would be only 50% of the exposure tool market even in 2012. That market would only be 1% of the $500B semiconductor industry, so the market for tools requiring $10B investment in the next 4 years would be $2.5B in 10 years. While the promoters of EUV technology may be correct that it is absolutely essential that the toolmakers buy in to the EUV program to ensure the prosperity of the semiconductor industry, it is equally clear that present business models cannot justify such commitments in the presence of other needs and uncertainties.
A joint evening session "Understanding molecular contamination in lithography" allowed participants in all four conferences to hear about purging and cleaning, increasingly menacing challenges at shorter wavelengths. Photoresist outgassing, in particular has frightened designers of 157nm and EUV systems. However, there has been tremendous progress in analyzing contamination processes and protecting optics with gas curtains and filters. It also turns out that a tiny amount of oxygen in the ambient gas allows 157nm light to clean off most contamination, with the significant exceptions of inorganic fluorides and silicates.