Taking IC manufacturing from 300mm pilot to production
05/01/2001
Nun-Sian Tsai, Taiwan Semiconductor Manufacturing Company, Hsinchu, Taiwan
overview
After delivering customer "first silicon" on 300mm wafers in 2000, today TSMC is actively processing customer designs on 300mm. In addition, construction is ongoing of its two full 300mm-production facilities that will receive equipment this year. In the longer term, the company is committed to 300mm manufacturing in all of its new facilities.
The transition to 300mm wafers is a costly one for the semiconductor industry. Its promise, however, lies in the ability to provide a cost-efficient answer for tomorrow's capacity demands. The transition to 300mm is so important that every major wafer foundry company is now dedicating a majority of its capital resources to the development of 300mm fabs.
At $2 billion or more per fab, it is sometimes hard to think of a 300mm manufacturing facility as being cost-efficient, but it will be if all goes as planned. With the ability to handle up to 2.5 times the number of die compared to a 200mm wafer, and with a 2.5 times yield improvement, the unit IC cost of a 300mm wafer could be reduced by 30% within the next two to three years. Over the life of a fab, this will translate to significant savings for the semiconductor community.
Still, getting to this level of cost-efficiency in a production mode will mean overcoming significant challenges on both a technical and logistics level. We will explore these issues here and discuss some of the things that we are doing at Taiwan Semiconductor Manufacturing Company (TSMC) to resolve them.
As the world's largest foundry, TSMC is aggressively moving to 300mm manufacturing. Already, we have delivered production 300mm wafers to several customers using the 4500 wafer/month capacity of our 300mm pilot line located in Fab 6 at Tainan. In addition, we are constructing two full-scale 300mm-production facilities: Fab 12 in Hsin-Chu and Fab 14 in Tainan. We will determine the equipment set for these fabs in 2Q2001. When completed in the next few years, these fabs will be capable of producing about 30,000 wafers/month each, dramatically increasing TSMC's manufacturing capabilities. Because of our industry-leading partnerships with equipment vendors and contractors, we feel confident that we shall succeed with our transition to 300mm.
Perhaps the easiest way to illustrate the business and technology decisions that are being made with respect to 300mm technology is to look at them in light of five important criteria: wafer productivity, risk mitigation, cost control, quality control, and materials handling.
Wafer productivity
Productivity is a key factor in almost any business or technology investment decision. So the crucial question is whether 300mm fabs will really deliver the productivity gains the industry needs. A realistic assessment is essential.
According to recent data from the equipment industry, wafer per hour (WPH) values of 300mm tools range from 70% to 90% of their 200mm counterparts, except for furnaces and photolithography tools (Table 1). This reduction in WPH is directly due to the larger wafer size, creating a need for slightly longer handling and stabilization periods.
 Figure 1. A proud crew celebrates the first installation of ASML's TWINSCAN 300mm lithography system at TSMC. |
Obviously, even if the industry reaches its three-to-four-year goals for wafer throughput, 300mm tools may on average only reach 80% to 90% of their 200mm counterparts. Thus, from the WPH point of view, the productivity of 300mm tools is inferior to that of the 200mm tools. Bringing these tools to the same or better productivity levels will be an ongoing challenge, but we must keep in mind that a 300mm wafer has 2.25 times more silicon real estate than a 200mm wafer. While the actual number of ICs that this real estate will support depends on die size and photolithography layout, we are confident that 300mm wafers will provide 2.2 to 2.5 times the number of die available from a 200mm wafer. Overall then, even with less wafer throughput than 200mm, 300mm wafers should be able to deliver superior productivity as measured in die/wafer. Builders of 300mm fabs will remain vigilant concerning 300mm-tool throughput, however.
Lithography throughput is the most critical; cost gains will not be achieved if lithography throughput cannot meet its forecast.
300mm thermal processing
Thermal processing of 300mm wafers provides an interesting analysis of the tradeoffs that surround tool throughput. Processing 300mm wafers in a batch furnace yields lower throughput because of smaller batch sizes and slower temperature ramping rates necessary to avoid costly slip lines or defects in the larger wafers. Currently, the 300mm WPH value for furnaces is around 60% to 70% of 200mm systems and it is unlikely that these will improve dramatically.
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While single-wafer thermal processing is not yet well established, it may find increasing application in 300mm fabs. Single-wafer processing appears to offer technical and strategic advantages for foundries, including defect control, performance for advanced technology, thermal budget minimization, integrated gate oxide processing, lower cost for thin films, and cycle time improvements. Along with these advantages, there is a lot to be said for reducing the risks associated with placing a batch of 300mm wafers into a conventional furnace (i.e., considering the cost of 300mm wafers and the amount of product each contains).
Consider just cycle time for thermal processing and what it means to a wafer foundry. TSMC's calculations point toward a need for 50% reduction in cycle time in the diffusion area when fabricating 180nm logic products. Foundries build their business on responsiveness to customers who typically need to verify their designs in silicon as early as possible. Any reduction in turnaround time is a competitive advantage. For example, according to our calculations, single wafer thermal processing for diffusion, in a generic 180nm-logic process, could result in a 72% reduction in process time.
Furthermore, there are potential performance gains that can be realized from single-wafer thermal processing of 300mm wafers. For example, processed through a single-wafer thermal system, wafers have a shorter thermal history and therefore less threshold-voltage shift due to dopant diffusion.
We must also consider, however, that there are some tradeoffs associated with single-wafer thermal processing. Significant device tuning is required, since thermal history changes dramatically, and the properties of single-wafer films may be very different from those from established batch processes. Moreover, single-wafer techniques may not offer much of an advantage in some thermal processes, such as film densification and metal alloying. Clearly, it is unlikely that we will switch every thermal process step to single-wafer processing with 300mm, but single-wafer processing is important for an efficient, cost-effective, and high-quality 300mm-manufacturing environment.
Risk mitigation
There are many technical risks associated with a project the size of switching to 300mm wafers, so at TSMC we have focused on mitigating these concerns.
Poor yield is our number-one risk. Simply stated, high yield requires us to do things right. Manufacturability for high-volume production and process control is an associated risk. With 200mm wafer processing, we learned that issues such as plasma etch conditions, process chamber conditions, and CMP dishing and erosion, etc., were very important. In our transition to 300mm manufacturing, we have carefully addressed how we handle these sensitive issues. To mitigate the risk, we have focused on porting 200mm recipes with a long-term, high-volume manufacturing history to our first 300mm tools.
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While the use of 200mm recipes seems fairly straightforward, part of the risk management is in our relationships with tool suppliers. For some tool sets, scaling chamber designs from 200mm to 300mm was not linear; this created a potentially serious problem. It meant that suppliers had to redevelop recipes for some 300mm chambers, something that often required more detail than they were initially aware of. In addition, it required better tool reliability tests for new 300mm tool components and parts.
One of the principal measures of manufacturing yield is defect density. To mitigate defect issues, and to reduce the overall cost of the transition to 300mm technology, we began our Fab 6 300mm pilot line using well-known 180nm TSMC technology. This accelerated the learning curve and helped us to isolate defectivity issues more readily. To date, we have not seen any major issues in transferring our 180nm process from 200mm to 300mm wafers. One probable reason for this is that the mechanisms of 200mm and 300mm tools are similar, so comparable numbers of particles tend to fall on wafers of either size. In fact, our data reflects that the absolute number of particles will be about the same for both wafer sizes, but because 300mm wafers have a larger area, defect density will be only 40% for 300mm wafers. Overall, in terms of the number of good die produced, the yield and productivity of 300mm wafers should be much better than that of 200mm wafers.
Moving forward, we do anticipate some challenges with defects as we integrate new processes onto our 300mm line.
Currently, work is under way on 130nm technology where our experience is relatively short. In addition, with this technology we will be using copper interconnects and low-k dielectrics, introducing layers of additional challenges.
We have found that risk mitigation works in all stages of the manufacturing process. For example, TSMC has selected the ASML TWINSCAN scanner for 300mm-wafer production (Fig. 1). The alignment methodology is different from previous models, as the new scanner uses transmission image sensor (TIS) markers for reticle alignment. However, TSMC also uses ASML scanners for 200mm wafers, where the mask alignment system is identical to the new system, except for the TIS markers. To mitigate the transition risk, TSMC has added the TIS markers to masks used for 200mm wafer manufacturing, allowing the same set of masks to be transferred to the 300mm production environment (i.e., all new mask for <180nm technologies, regardless of wafer size, will include the TIS marker). This is a major advantage, because in early stages the masks can be verified using 200mm wafers before the same mask set is used for making 300mm wafers.
Indeed, risk mitigation is also behind our reason for starting with a 300mm pilot line, rather than beginning with a new 300mm fab. Our pilot line has provided a "real-world" setting for production trials of equipment and materials to be used for high-volume manufacturing. It began with our 180nm-core logic process that we were using on our 200mm-wafer fabrication lines, and where possible, followed the baseline recipes from our 200mm fab. In situations where a direct "process copy" was not feasible, the pilot line experience revealed needed modifications, their costs, and their degree of complexity. Now, our 300mm pilot line is a template that will hasten the installation of full 300mm fabs.
Because the maturity of many 300mm tools has not been completely verified at any production facility, we found that it was imperative to work closely with equipment vendors, particularly those who had to deliver and support the most critical components. Some of the riskiest factors in the 300mm cost-benefit equation are those pertaining to production equipment. As in the 200mm cost model, equipment costs dominate the cost of implementing 300mm technology. The partnership model involves shared risk, and a level of cooperation that goes beyond anything experienced in earlier manufacturing start-ups. Each partner's responsibilities must be clearly defined. Exchanging proprietary information is a necessary part of the arrangement.
Cost control
Cost issues are closely associated with risk mitigation. High throughput with low risk is of course good, but can it be had at a price that allows profits? Both tool costs and materials costs affect this evaluation.
Currently the capital cost for all 300mm tools combined falls somewhere between 1.2 to 2.0 times that of an equivalent 200mm tool-set. So, given the 2.25x 200-to-300mm silicon real estate improvement, there is a measurable cost advantage for 300mm fabrication lines.
Unfortunately, direct materials cost (i.e., 300mm silicon wafers) reverses this advantage. At present, the price of a 300mm wafer is about seven or eight times that of a 200mm wafer, far exceeding the 2.25x multiplier. So we are looking forward to normal market dynamics bringing down prices as the demand for 300mm wafers increases. Some silicon wafer suppliers predict that 300mm wafer prices will fall to 3.5 times that of a 200mm wafer within three years.
Perhaps more of a concern is the potential for a shortage of 300mm wafers. At TSMC, we believe that wafermakers are not being aggressive enough in their investments. It is our view that the transition to 300mm wafers will occur much more rapidly than was expected even a year ago. It is therefore important to work closely with wafer vendors to clarify delivery commitments and quality standards long before wafers are needed. So far, we have good success with wafer suppliers in engineering problems and cost reduction projects.
To reduce 300mm wafer costs further, there are proposals for relaxing some specifications. Possible changes include the elimination of backside films, less stringent requirements for crystal originated precipitated defects (COPs), thinner epitaxial silicon layers, and more. TSMC has actively participated in all these areas.
For indirect material costs, such as the chemicals, gases, and equipment consumables, the goal for 300mm wafer processing is to limit them to 2.5 times that of equivalent 200mm expenses. This has not yet been achieved, however, because of the small quantity usage in 300mm. While some materials are expected to reach the 2.5x goal, others, such as quartz furnace tubes, may cost 3.5-4x the 200mm counterparts. So, extending the lifetime of these more expensive consumables is a high priority.
Quality control
Quality control in a volume production environment is a key function that must be given the highest consideration. For example, in our initial 300mm production, using well-characterized 180nm process technology, we are requiring first order, one-sigma process uniformities and process windows similar to what we achieved with 200mm wafers. Simply stated, we cannot let our company's end-product quality deteriorate as a result of the change to 300mm wafers.
 Figure 2. TSMC's wafer sampling points that allow more accurate transition from 200mm to 300mm processing. |
One element of our effort to monitor quality control is our sampling plan for "averaged out of quality" levels (AOQL); the statistical results of this metric for our 300mm wafer line must match or exceed that of our 200mm lines. To accommodate the increase in wafer size, we modified the number of sample points and the sampling locations with a new scheme where each sample point represents a comparable amount of physical real estate, whether the wafer is 200mm or 300mm (Fig. 2). In effect, the 5-9 sites sampled on an 200mm wafer become 9-17 sites on a 300mm wafer. This plan also provides information on wafer-edge quality, which we consider critical for the 200-to-300mm conversion. With this data, we require a 95% confidence level. In addition, to facilitate yield analysis and yield correlation to wafer processing, the same sampling plan and wafer locations are used for all measurements: off-line, in-line, wafer acceptance test, and quality control inspection.
In any new IC manufacturing efforts, systematic defects are primarily due to process integration problems and require time to be effectively resolved. These problems can arise at any stage in the process, from photoresist to etch and strip. Integration defects of just a few percentage points add up alarmingly fast, however, when you consider the number of steps in an IC manufacturing process. So we are looking to equipment vendors to play a major role in resolving these issues.
From our earliest demonstration lots, we have achieved better yields than were possible using 200mm equipment, which is to be expected considering the overall reduction in particle density (discussed above). There is still much room for improvement, though. Today, our focus is on eliminating a few percentage points of yield loss resulting from systematic defects.
Our requirements for new capabilities and solutions for 300mm yield management and process control are focused primarily on equipment parameter control. Ideally, we should have the ability to collect data and statistics that will enable us to develop a methodology to improve yield and reduce sporadic scrap.
Information technology should play a very prominent role in networking all of this information together. Correlation of data is important and a lot of work needs to be done in this area. Tools today provide a lot more valuable information, and correlation of information such as electrical faults to physical defects is critical. This is an area that should grow within the semiconductor industry.
Ultimately, we plan to develop and use advanced computer integration manufacturing (CIM) and manufacturing execution systems (MES) to perform single-wafer tracking and yield correlation for our 300mm wafer fab lines. Our plan is to add this capability in steps over the next few years.
Materials handling
Each 300mm wafer going through the fab represents more time and money invested than for a 200mm wafer, so wafer-handling systems and tracking systems within the fab area must be rock-solid, reliable, and foolproof.
At TSMC we have relied on minienvironment - i.e, standard mechanical interface (SMIF) - technology in our 200mm fab lines. This same approach will be carried over to our 300mm facilities, although not necessarily using the same minienvironment vendors, for two very compelling reasons. Cleanliness and defect-control requirements for advanced products make it almost impossible to process wafers in a conventional cleanroom without the minienvironment, and the costs for cleanroom facilities and operational costs for airflow are significantly lower when using minienvironments.
We have decided on the Semi standard front opening unified pod (FOUP) for our 300mm fabrication lines. The FOUP is similar to the proven SMIF box used on our 200mm lines. Because the two environments are so similar, characteristics such as out-gassing are already well understood.
As for our automated materials handling system (AMHS), which is required because a full cassette of 300mm wafers is too heavy for an operator to carry safely by hand, we are selecting equipment that adheres to the International Sematech interoperability guidelines. We feel that this decision will circumvent docking and interface compatibility issues, saving integration and maintenance costs.
For intrabay automation, TSMC has chosen to link minienvironments using overhead transport systems. This will reduce the number of operators in the cleanroom.
Finally, our 300mm-wafer lot tracking will use SMART-Tag technology, which offers excellent visual and factory-automation display capabilities. With the SMART-Tag, both the human operator and the manufacturing tool can quickly identify the lot and learn its routing and priority status. The SMART-Tag information also hastens recovery from power outages and other wafer movement stops.
From TSMC's 300mm overlook
By early 2000, many tools required for 300mm-wafer processing were sufficiently developed to let us add a 300mm pilot line to our Fab 6. This pilot line allowed us to establish tool compliance with our process technologies, and to evaluate production changes and solutions for the automation of volume production handling.
Rapid deployment of a 300mm equipment set required minimal changes. While the 300mm pilot line occupies a certain percentage of the Fab 6 ballroom, this room was already set aside and the addition of new equipment caused no disruption of 200mm production there. Initially, the pilot line used 180nm CMOS technology for both logic and SRAM products. However, our plan is to expand to 130nm capability and mixed signal products by the middle of 2001.
Our extremely supportive equipment suppliers have provided valuable assistance during pilot line evaluation. Many were eager to install their systems in the Fab 6 pilot line, since it would help determine which 300mm tools would be installed in our future plants (and those of the rest of the industry).
Our 300mm-tool installation started July 5, 2000, two months after Fab 6's dedication, with a goal of delivering fully functional chips by the end of 2000. Our achievement of this goal - delivering the foundry industry's first functional 300mm wafers to customers in 2000 - clearly sets an industry benchmark for the cycle from tool installation through first silicon.
The most encouraging footnote to Fab 6 is that we will be able to extend our success into 300mm lines and into all our future fabs. We expect to begin installing equipment in Fab 12 in Hsin-Chu shortly, and Fab 14, across the street from Fab 6, will be ready for initial production early in 2002. All those who expect to contribute to future foundry demand can take comfort from that.
I think that 300mm fabs will be more productive and have greater return on investment than 200mm fabs after 2002 because there is room for higher profitability and higher yield. With time-to-volume requirements increasing all the time, the larger number of die/wafer will be a significant strategic advantage. Our extensive experience in yield learning and process control, combined with risk mitigation procedures, will help us to achieve this capability.
Acknowledgments
SMIF and SMART-Tag are trademarks of Asyst Technologies.
Nun-Sian Tsai received his PhD in materials science from MIT. He is senior director of the 300mm pilot line project at TSMC, 1, Nan-Ke North Rd., Shan-Hua, Tainan, Taiwan; ph 886/6-5091007, fax 886/6-5052088, e-mail [email protected].