Issue



Jet ECD plating and seed layers for sub-0.10µm Cu interconnects


05/01/2001







U. Cohen, G. Tzanavaras, Jets Technology, Santa Clara, Californi


Figure 1. The anode/jet assembly of the Jets Technology plating cell (US patent 5,421,987).
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overview
Jet electrochemical deposition plating [1-2] has shown excellent capability for void-free Cu filling of narrow openings with very large aspect ratios. JECD facilitates high-speed plating, with fully bright deposits at higher speeds. Additional "leveler" additives and pulse plating are not necessary for the elimination of spikes, bumps, or humps. JECD also provides wide process latitude. Here we suggest an enhanced inhibition model explaining the mechanism and the beneficial effects of JECD. We also report an innovative multiple-Cu seed layer [2-3] combining at least one PVD and one CVD Cu layer.

Future copper interconnect generations will require void-free filling of very narrow (<0.10µm) and deep (>1.0µm) vias and trenches with large aspect ratios (>10:1). Due to its ability to accomplish void-free filling of narrow openings at reasonable rates, electrochemical deposition (ECD) is currently the technology of choice for Cu filling. However, in order to extend the ECD technology from the current smallest filled openings of 0.18-0.25µm to future generations requiring openings below 0.10-0.13µm, both the ECD and the seed layer technologies will have to overcome considerable challenges [2, 4-17].

Due to a higher electric field at the top corners of openings, the local current density (and plating rate) is higher at the top corners, leading to faster growth and pinching-off of the top corners. Also, during electroplating, the relatively stagnant electrolyte inside the opening results in depletion and poor replenishment of the plating ions there. This leads to a slower plating rate inside the opening than outside of it. This depletion is more severe at the bottom of the opening, and less severe near the top corners. The plating ion concentration gradient produces increasing concentration polarization and decreasing plating rate along the depth of the opening. These inherent electroplating problems become more severe with decreasing width and increasing aspect ratio (AR) of the openings.


Figure 2. AFM profile of a wafer plated with a conventional plating tool, showing a transition from the field to 0.35µm spaces and lines. There is a spike and an offset at the boundary.
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Commercial electroplating baths, such as acidic copper sulfate baths, include proprietary surface active "brightening" and/or "leveling" additives. These comprise organic compounds with functional sulfur and/or nitrogen groups that adsorb onto the growth sites of the depositing metal surface, thereby inhibiting (or suppressing) the metal deposition rate. The adsorption and its associated inhibition lead to smaller grains of the depositing metal, thus producing smoother and brighter deposits. Leveling is obtained by higher concentration of the inhibitor at the tips of protrusions sticking into the diffusion layer, thereby inhibiting their growth. As a result, inhibition is stronger at protrusions, compared with the flat surface.

In much the same way, the relatively stagnant electrolyte inside narrow openings results in poor replenishment of the inhibitor there, leading to reduced inhibition and faster growth inside the openings.

Inhibition is stronger at the top corners of openings and at the top outside surface (field), compared with inside the openings. Reduced inhibition inside narrow openings speeds up the plating rate there, relative to the field, thus facilitating void-free filling of narrow openings with large aspect ratios.

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Figure 3. SEM photos of cleaved samples, showing transitions from the field to a trench array for samples plated at a) 15mA/cm2 (0.35µm/min) and b) 120mA/cm2 (2.8µm/min).

In order to achieve void-free filling of narrow openings, the beneficial effect of inhibition gradients must overcome the intrinsic void formation due to a) higher current density at the top corners; and b) decreasing plating rate along the depth of the openings due to concentration gradients of the plating ions there.

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Figure 4. Inhibition model of the brightening mechanism. The lower portion shows (central) protrusions for different current densities, while the upper portion shows a schematic plot of the inhibitor concentration profiles for the same current densities.

As openings get narrower, and the aspect ratio gets larger, void-free ECD filling becomes increasingly difficult to control. The process latitude, such as the useful concentration range of the additives and/or plating rate, becomes very tight and hard to control [6, 17-18]. Also, the usual plating rate is relatively slow, about 0.3-0.4µm/min, thereby limiting the throughput of single-wafer plating modules. In addition, due to their surface roughness, the usual plated wafers appear as matte or semi-matte to the eye. This roughness impairs ensuing CMP steps. In particular, topographical bumps or humps over the openings, and spikes and steps of the plated layer at boundaries between the field and arrays of narrow openings may cause excessive erosion and dishing during CMP steps that follow [2, 14, 17, 19].

Here we report on void-free Cu filling with the use of jet ECD (JECD), a process that addresses the conventional ECD drawbacks. Several models and simulations have been proposed to explain the superfilling by ECD in the presence of additives [4, 7-8, 13, 15, 17, 20-22]. We suggest here an enhanced inhibition model to explain the beneficial effects of JECD on the superfilling mechanism.

Challenges with conventional PVD and CVD seed layers
Conventional Cu seed layers, obtained by either physical vapor deposition (PVD) or chemical vapor deposition (CVD) techniques, suffer from significant shortcomings [2-5, 9, 11-12, 16]. The PVD techniques, while providing adequate Cu thickness on the top field, do not always provide adequate step coverage of sidewalls inside very narrow openings. Discontinuous step coverage on the sidewalls or bottom of the openings leads to voids [4, 9, 12, 16].

On the other hand, CVD techniques, while providing conformal seed layers with adequate step coverage inside very narrow openings, fail to provide enough thickness on the top field outside the openings. For adequate surface conduction, a sufficiently thick Cu seed layer on the top field is needed. Good surface conduction is required in order to achieve void-free filling across the wafer, and for good plating uniformity across the wafer. In order to minimize the voltage drop along the radius during the initial plating stages, the thickness of the Cu seed layer should be at least 1000Å on the field. However, the conformal CVD (or electroless) techniques, when designed to deposit at least 1000Å seed layer on the field, pinch off the top corners of openings smaller than about 0.18µm, thereby failing to leave enough space for the ECD.

Jet ECD
Figure 1 shows the anode/jet assembly of the Jets Technology plating cell [1]. During plating, the wafer faces the anode/jet assembly a short distance (about 1 in.) from it. Either the wafer or the anode/jet assembly rotates in order to improve uniformity. Both the wafer and the anode/jet assembly are immersed in the electrolyte. The wafers can be positioned vertically or horizontally, and face up or face down.

The jets' impingement on the wafer's surface creates vigorous turbulent agitation, thereby significantly reducing the diffusion layer thickness. The strong agitation facilitates a significant increase of the plating rate without "burning" the deposit. We found that we could safely increase the plating rate to 2.8µm/min, without any negative effects. (This is about 8x faster than a typical plating rate of about 0.35µm/min.) We also observed that the surface becomes brighter by increasing the plating rate.

At 2.8µm/min, the wafer appears fully bright. The appearance, however, is also a function of the seed layer.

Figure 2 shows an atomic force microscope (AFM) trace of a wafer plated by a leading vendor's conventional ECD tool. The trace was taken over a transition from the flat field to an array of trenches of 0.35/0.35µm lines/spaces. The wafer was plated to a nominal thickness of 1.5µm. Note the large spike (~520nm) and an elevation step (~250nm) at the transition. For comparison, Figs. 3a and 3b shows photos of two cleaved samples plated by the JECD tool, with two different plating rates. While the lower plating rate (Fig. 3a) shows a step of about 140nm at the field/array boundary, the sample plated at the higher rate (Fig. 3b) shows no transition step at all.

The surface roughness of JECD plated samples also improves with plating rate. AFM measurement of the mean surface roughness (Ra) of a low current (15mA/cm2) sample was 11.2nm, and at the higher current (120mA/cm2), it was only 7.3nm. It is important to note that the JECD plating did not require a third component "leveler" organic additive, or the use of a complex pulse or periodic reversal pulse plating, in order to eliminate the spikes and steps common in conventional ECD plating. In general, a leveler additive greatly complicates the required bath analysis and control [4, 17]. It may also result in top center voids and poor filling of larger features [4]. Pulse plating, and, in particular, periodic reversal (PR) plating, decreases the throughput and further complicates the required control [14, 19]. It may also result in larger grains, a rougher surface, and a longer self-anneal time of the plated Cu film [19].

Plating inhibition model
Figure 4 suggests an inhibition model to explain the increased brightness with the plating rate. At low current density (15mA/cm2), there is only a small depletion (DC15) of the inhibitor at the wafer's interface. As a result, there is very little or no inhibition differentiation between a growing protrusion and the flat surface. Due to higher concentration of the plating ions ahead of the flat interface, protrusions (after exceeding a critical size) can continue to grow faster than the flat surface. This leads to amplification of the protrusions and roughening of the surface.

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Figure 5. Cleaved samples plated at 120mA/cm2 showing superfilled trenches after a) partial filling and b) complete filling.

At a high plating rate, the high current density (105mA/cm2) creates larger depletion (DeltaC105 >> DeltaC15) of the inhibitor at the (flat) wafer interface. The tip of a growing protrusion "sees" a significantly larger concentration of the inhibitor than the flat surface. Protrusions that reach into the diffusion layer are suppressed (or inhibited) by the higher concentration of the inhibitor ahead of the flat surface. The flat surface, on the other hand, "sees" deeper depletion (or lower concentration) of the inhibitor as the current density increases, thus enhancing its deposition rate, relative to the protrusions. The enhanced suppression of protrusions at the higher current densities leads to smoother and brighter deposits [2, 19].

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Figure 6. Sample trenches plated with JECD: a) 0.175µm wide (at the bottom) and 1.4µm deep (AR ~8:1); and b) a lightly etched cross section 0.05µm wide (at the bottom) and 1.41µm deep (AR ~28:1).

The commonly encountered topographical bumps are due to coalescence of individual microbumps above the openings (or above spaces) into larger humps. In the lack of sufficient leveling, the coalesced humps continue to amplify and grow faster than the flat field, since they "see" a larger concentration of the plating ions ahead of the flat field. We found that, using JECD with decreasing opening width, the size of microbumps decreases, and their location often shifts from above openings to above spaces. These findings refute any "memory" effect, in which the plating rate above filled openings somehow mimics the plating rate inside the openings, even after they have been filled. As current increases, leveling becomes more prevalent, thus reducing or eliminating the bumps and humps [2, 19].

The most important factor for leveling (for a given chemistry of additives and their bulk concentrations) is to create a large concentration gradient across the diffusion layer (DCinh/DX). This is achieved by increasing the current density (larger DCinh) and by the vigorous agitation (smaller DX) produced by the jets.

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Figure 7. Conventional Cu seed layers: a) PVD seed layer with combined (Cu plus barrier) thickness of 2000Å on the field and 150Å on the lower sidewalls, and vias 0.25µm wide and 1.9µm deep (AR ~7.6:1); and b) CVD seed layer with combined (Cu plus barrier) thickness of 450Å on the field and sidewalls, and trenches 0.13µm wide and 1.4µm deep (AR ~10.8:1).

The mechanism of void-free filling of narrow trenches and vias ("superfill") may be viewed as the reverse of suppression of protrusions. In order to create more inhibition on the top flat surface (field) than inside the openings, a larger concentration of the inhibitor, Cinh, must be present at the field than inside the openings. In other words, there must be a large DCinh between the field and the inside of the openings. While the jets produce vigorous agitation at the flat surface (field), the solution inside narrow openings is virtually stagnant. As a result, the jets considerably reduce the thickness of the diffusion layer, DX, thereby enhancing the supply of inhibitor to the field, which in turn slows down the plating rate there.

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Figure 8. New PVD/CVD seed layer shown with a) 30° tilt, and b) no tilt. The seed layer is 450Å (total) on the sidewalls and 1900Å on the field. Trenches are 0.10µm wide and 1.4µm deep (AR ~14:1).

Meanwhile, due to the stagnant and small volume (and large area/volume ratio) of the solution inside the opening, the plating consumes and depletes the inhibitor there. This depletion establishes concentration gradients of the inhibitor along the sidewalls (depth) of the openings, with the maximum depletion at the bottom. The maximum plating rate is therefore established at the bottom of the opening, with a gradual decrease from the bottom toward the top corners of the opening. This facilitates progressive sealing from bottom to top (superfilling), without seams or voids. Figure 5 shows cleaved samples filled by the superfill mechanism. The growth profiles on the bottom and sidewalls correspond to the plating rate profiles inside the trenches. The plating rate is fastest at the bottom (maximum depletion and minimum inhibition) and is slowest at the top (minimum depletion and maximum inhibition) of the openings.

The model and the experimental results imply that, in very narrow openings (with a large AR), most of the filling is due to lateral growth components, about normal to the sidewalls. This explains why narrower openings fill earlier than wider openings. Almost one half of the upper width of the opening has to grow laterally, in order to seal the opening. The sealing of the opening proceeds - like a zipper - from bottom to top [7-8, 13, 15, 20, 22]. It is the plating rate gradients, along the depth of the openings that facilitate void-free filling of narrow openings.

As openings get narrower, the ratio (R) of surface area (A) to volume (V) of the openings becomes larger. This ratio is reciprocal to D, the diameter of vias or width of trenches:

R = A/V µ 1/D

A larger ratio A/V results in faster depletion of the inhibitor inside the openings. In other words, it takes less time (keeping all other parameters the same) to establish the inhibitor's depletion gradients inside the openings. This, in turn, results in thinner transitional conformal growth on the bottom and sidewalls prior to superfill commencement. Thick conformal (or nonconformal) layers on the sidewalls lead to deleterious seam-voids in the center of trenches or vias [7-8, 17]. The thickness of the sidewall layers must be minimized in order to achieve void-free filling. Even complete depletion inside the openings will not produce void-free filling, however, unless there is sufficient supply of inhibitor to the top field. Without the latter, DCinh between the field and the inside of the openings becomes too small to enable the superfill mechanism. This is where JECD becomes beneficial. The jets considerably improve the supply of inhibitor to the field compared with conventional plating, thus significantly increasing DCinh. The larger DCinh produced by the jets enables superfilling of even the narrowest (as well as the wider) openings, with wider process latitude.

The agitation of the jets increases the concentration gradients of the inhibitor, DCinh/Dh, along the depth (h) of the opening, thus leading to corresponding inhibition gradients from the field to the bottom of the opening. The larger these gradients, the more efficient and prevalent the superfill mechanism. At large enough gradients, even the narrowest openings can be filled without voids. At the same time, increasing these gradients also facilitates wider process latitude. We found that, utilizing JECD, we were able to use a very wide range of plating rates (0.35-2.8µm/min) and vary the nominal additive concentrations by more than 100%, without negative effects.

Figures 6a and 6b are scanning electron microscopy (SEM) photographs of cleaved samples plated by the JECD tool. The most demanding void-free filled trenches (Fig. 6b) were ~0.05µm wide (at their bottom) and ~1.41µm deep (AR ~28:1).

Seed layers
Conventional Cu seed layers are deposited by nonconformal PVD (Fig. 7a) and conformal CVD (Fig. 7b) techniques. The combined thickness of the Cu seed plus barrier layers is only about 150Å on the lower sidewalls in Fig. 7a. A substantial fraction of this thickness (~100Å) is attributed to the barrier. Clearly, the remaining Cu thickness is inadequate to provide continuous coverage of the sidewalls. Attempts to fill such openings usually result in characteristic voids (extending to at least one wall) near the bottom or center of the openings [4-5, 9, 12, 16]. The combined thickness of the CVD Cu seed plus barrier layers (Fig. 7b) is about 500Å on the field and the bottom and sidewalls of the trench. While this seed layer provides excellent and uniform step coverage, it is too thin on the field for adequate surface conduction. Low surface conduction impairs plating uniformity and/or void-free filling across the wafer. Cu seed layer thickness should preferably be at least 1000Å on the field.

Figures 8a and 8b are cleaved samples coated with a multiple-Cu seed layer. The sample shown had a combined thickness (including the barrier) of ~450Å on the sidewalls and bottom, with uniform step coverage. The combined thickness of this sample was ~1900Å on the field. It was obtained by depositing ~250Å CVD Cu and ~1450Å PVD Cu layers. The trenches were ~0.10µm wide (at the bottom) and ~1.4µm deep (AR ~14:1).

In general, MOCVD Cu layers have poor nucleation and adhesion on the barrier [11-12]. These are probably due to interfacial oxides and/or carbides formed by reaction of the refractory metal barrier with the organo-copper precursors. In order to improve adhesion and nucleation, the preferred order of deposition is an initial PVD Cu layer, followed by a CVD Cu layer. It is also possible to deposit more than two Cu layers. For example, it is possible to start with a thin ("flash") PVD layer to improve adhesion and nucleation, followed by a CVD layer, and finally depositing a second (relatively thick) PVD layer to enhance the thickness on the field. This configuration minimizes overhangs prior to deposition of the CVD Cu layer. In all these cases, the PVD Cu thickness exceeds the CVD Cu thickness (on the field). The multiple-Cu seed layers provide adequate surface conduction in the field and excellent step coverage, while occupying the minimum space inside the openings [3]. They allow us to obtain void-free filling of the narrowest vias and trenches, at plating rates up to about 2.8µm/min. They greatly enhance the yield and reliability of the present generation (0.18-0.25µm) of Cu interconnects and provide a clear extendibility path to future generations, down to well below 0.10µm [2-3, 12].

Conclusion
We demonstrated the capability of JECD for void-free Cu filling of extremely narrow openings (down to 0.05mm) with very large aspect ratios (up to 28:1). The JECD process also facilitates plating speeds up to 8x faster than conventional plating. Fully bright deposits were obtained at higher plating rates, eliminating the deleterious spikes and elevation steps usually found after Cu plating. We also demonstrated preliminary results of innovative multiple-Cu seed layers that combine at PVD and CVD Cu layers. These seed layers provide uniform step coverage of the sidewalls and bottom of very narrow openings, while maintaining adequate thickness on the top flat field surface.

References

  1. G. Tzanavaras, U. Cohen, "Precision High Rate Electroplating Cell and Method," US Patent 5,421,987 (issued June 6, 1995).
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    Uri Cohen received his BS and MS degrees in chemistry and physical chemistry, respectively, from the Hebrew University, Israel, and his PhD in materials science and engineering from Stanford University. He has worked at Bell Laboratories, Technion Institute, Sperry-Univac, MPI/CDC, Velocidata, and as a consultant. He was also a founder of Silver Memories and ToroHead Inc. He is currently a general partner of Jets Technology, where he is involved in developing the JECD technology. He has more than 40 issued and pending patents, and has contributed to 40+ technical publications. Jets Technology, 3374 Victor Court, Santa Clara, CA 95054; ph 408/980-1700, fax 408/980-1948, e-mail [email protected].

    George Tzanavaras earned his BS in electromechanical engineering from the Technical Institute in Greece, and his MS equivalent in metallurgical engineering. He has worked at IBM, Tandem Computers, and as a consultant. He is founder of Advanced Memory Components Inc., where Jets Technology is presently located, and Gemini Magnetics Inc. He is currently a general partner of Jets Technology, where he is involved in developing the JECD technology. He has several US patents and publications and has filed many technical disclosures.