Technology News
04/01/2001
Spooky quantum physical force harnessed for MEMS
Physicists at Lucent Technologies' Bell Labs, Murray Hill, NJ, have made a microscopic seesaw that moves in response to a little-known but strong and pervasive force predicted by quantum mechanics. This experiment, which was reported in Science, shows that esoteric physical effects are important in designing nanoscale machines, which are 1000 times smaller than today's micromachines. It also suggests that such effects might be used to make extremely sensitive sensors in the future.
This work is part of Bell Labs' physicists' research into microelectromechanical systems (MEMS). Federico Capasso, physical research VP at Bell Labs and a member of the team that produced the seesaw, said, "We are using our expertise in MEMS to fashion creative experiments that illustrate what little-known quantum effects come into play in extremely small devices." Other Bell Labs physicists involved in the experiment were Ho Bun Chan, Vladimir Aksyuk, Rafael Kleiman, and David Bishop.
According to quantum mechanics, even empty space has a little energy (i.e., zero-point energy) associated with it. This picture is quite different from the classical understanding of a vacuum as completely empty space without any energy. In the quantum description, a vacuum is teeming with virtual photons that produce constantly oscillating electromagnetic fields. In 1948, Dutch physicist Hendrik Casimir predicted that this zero-point energy would produce an attractive force between uncharged parallel metallic plates that are very close together. This bizarre "Casimir force" was first measured precisely by physicists in 1997.
Bell Labs physicists recently realized that the Casimir force could be used to tilt a microscopic MEMS seesaw (see figure). They built the seesaw using a tiny metallized plate balanced on a hinge and kept parallel to the surface of a silicon chip. When a gold-plated sphere suspended on a wire was brought close to the seesaw — an experimental setup similar to the two parallel plates — the seesaw was attracted toward the sphere in agreement with Casimir's prediction. Their results show that quantum mechanical effects play a significant role in MEMS systems when the separation between components is in the nanometer range.
David Bishop, director of Bell Labs' micromechanics research said, "This experiment has opened up an entirely new sensitivity range for MEMS devices." (Bishop's team of MEMS researchers developed and recently began customer shipments of the Lucent WaveStar LambdaRouter, the world's first commercial all-optical switch capable of switching data at rates up to terabits/sec.) "In addition to making powerful optical switches with MEMS technology, we are using MEMS techniques to do heady scientific work that pushes the frontiers and may lead to wonderful [new] devices," Bishop said. — P.B.
Innovations needed for Cu/low-k integration
Low-k materials continue to be a bigger headache than originally envisioned. With many facilities working on Cu/low-k integration, more problems are being uncovered. Low-k damage due to etching and cleaning has been widely reported, but there are many other issues emerging, according to Bob Havemann of International Sematech/Texas Instruments. Havemann outlined his view of Cu/low-k integration in an invited talk at the American Vacuum Society (AVS) International Conference on Microelectronics and Interfaces held in Santa Clara in February.
One new problem with low-k dielectrics presented by Havemann is "poisoning" of deep-UV resists by low-k materials. When the low-k material comes in contact with the DUV resist, it can cause problems with the resist that are not well understood yet. All DUV resists are subject to this, and it is a very complicated problem — the many combinations of low-k materials and DUV photoresists show different effects.
Other low-k problems arise from mechanical properties. The strength of low-k materials, especially as porosity is added, is widely known as a concern for processes with physical stress involved, such as CMP and wire bonding. One subtlety in the issues related to physical structure, though, is the effect of porosity on film roughness. It has been found that a rough surface on the dielectric contributes to barrier film failure, making it critical to have the pore size as small as possible and uniform. Havemann did note that CVD barriers seem to be more forgiving of rough dielectrics, though.
A key metrology technique for evaluating pores in a film is positron annihilation lifetime spectroscopy, which determines the pore size and distribution. Tight control of pore size and distribution does not solve all of the problems, though, with porosity of any type increasing the coefficient of thermal expansion and decreasing the thermal conductivity of the material. A larger thermal mismatch among the materials present decreases the robustness of the structure, while a diminished capacity to transfer heat through the structure decreases the reliability because of faster electromigration. There is a Sematech program to make standard measurements of the material properties of low-k dielectric films so that these and other properties can be better measured and understood. New interconnect reliability measurements should also be done, according to Havemann, including bias temperature stress. Performance under bias is appropriate for more than just gates in the devices as everything scales down.
For barrier films in Cu/low-k structures, a 7nm-thick layer will be needed in 2008, which the 2000 update to the ITRS cites as the 60nm node, instead of the 70nm node identified in the 1999 ITRS.
Havemann expected CVD or ALCVD to replace PVD at that point for barrier films, with ALCVD being used beyond that. Havemann also had some predictions for the seed and film layers at other technology nodes, with CVD replacing PVD for the seed layer at the 90nm node, and CVD replacing electroplating for the film at the 60nm node.
Along with all of these processing issues slowing down low-k integration, there is still a fundamental question about the ultimate effectiveness of minimizing the dielectric constant of the intralayer dielectric. For example, even with an air gap (k = 1) between two metal lines, the effective dielectric constant (keff) will be something like 1.5, according to Havemann. With solid dielectric layers (including barriers of SiC or other materials) between the metal layers, the effect on the electromagnetic fields between metal lines results in higher line-to-line capacitance. So, the asymptote for the lowest possible keff will be at a level somewhat above 1 unless there is a significantly new approach to this challenge. — J.D.
Kopin signs with Rockwell to develop carbon-doped InP-based HBT technology
Kopin Corp., Taunton, MA, has developed technology for carbon-doped indium phosphide (InP) based heterojunction bipolar transistors (HBTs). These transistors are considered a crucial technology for components used in wireless and high-speed optical communications systems. John C.C. Fan, Kopin's president and CEO, said, "InP is the next-generation semiconductor after gallium arsenide (GaAs). Compared to GaAs HBTs, InP HBTs demonstrate superior speed, operating voltage, power efficiency, and thermal properties."
At Kopin, engineers are growing carbon-doped InP HBTs using organometallic chemical vapor deposition (OMCVD) systems, the preferred technique for large-scale manufacturing. While the patent-pending process is proprietary, it has apparently overcome previous difficulties to incorporate sufficient quantities of carbon into InP HBTs, especially by OMCVD. Although beryllium-doped InP HBTs have been grown by molecular beam epitaxy (MBE), carbon-doped HBTs are preferable because carbon is a more stable dopant. Roger E. Welser, Kopin's director of transistor technology, says, "We have achieved active carbon-doping levels exceeding 1 x 1019/cm3, a critical threshold for many circuit applications. In addition, we are steadily increasing the doping level for even higher-speed circuits. The transistor characteristics of large-area InP HBTs grown and fabricated at Kopin are excellent, suggesting very high material quality is obtained by our OMCVD process."
Kopin officials believe that this breakthrough will enable a new generation of high-performance, reliable, cost-effective InP HBT circuits for a wide variety of applications, including 40Gb/sec fiber optic circuits and efficient power amplifiers for third-generation wireless phones. "The addition of InP HBTs to our product mix provides our customers and partners with a wider selection of devices," said Fan. "We are now beginning to sample InP HBTs with select partners."
In related news, Kopin and Rockwell Science Center (RSC), Thousand Oaks, CA, have established a joint development agreement designed to accelerate InP HBT development for commercial applications. Kopin will develop InP-based HBT structures and RSC will create processing technologies for devices and circuits and establish the long-term reliability of InP HBTs.
Fan notes "RSC pioneered the development of HBT technology, and we are very pleased to partner with them. RSC combines an excellent team of R&D scientists and engineers with world-class expertise in high-speed devices and circuits."
Several years ago, Kopin and Rockwell co-developed commercial GaAs-based HBT power amplifiers for wireless phones. "We are delighted to combine forces again as we focus on accelerating the introduction of InP HBTs into the commercial marketplace," said Fan. "This agreement comes only a month after our introduction of carbon-doped InP HBTs for use in wireless and high-speed optical communication. Our partnership with RSC will provide rapid advances in the fundamental material and device technologies, while Kopin will continue to work with its customers on commercial applications."
RSC director Derek Cheung, reportedly one of the world's foremost experts in high-speed devices and circuits, said, "InP-based HBTs are becoming the most exciting frontier for ultra-high-speed circuits. Kopin's success in incorporating active carbon doping in InP-based HBTs by OMCVD is a very important advance. Our two teams have worked successfully on GaAs-based HBTs, and we are now combining our resources to move InP-based HBTs into commercial readiness within a year." — P.B.
A glimpse of metrology beyond CD-SEM
SPIE Microlithography attendees got a glimpse of a metrology technology that may represent the future. For a start, this new capability seems uniquely poised to better facilitate the transition to the 130nm-technology node because it overcomes some of the limitations associated with scanning electron microscopy (SEM) and optical technologies. At SPIE, FEI Co., Hillsboro, OR, unveiled its dual beam technology dubbed Metra. Dual beam refers to the combination of in situ focused ion bean (FIB) milling and SEM imaging that generates 3-D metrology data from one sacrificial die on a production wafer that continues through production (Fig. 1). Metra is available in both 200mm and 300mm versions with automated wafer handling, pattern recognition, and statistical data collection and interpretation. FEI's Nick Dawes, director of structural process control products, told Solid State Technology, "In a nutshell, this technology looks at any layer of interest and provides 3-D metrology relationships even to previously fabricated layers. We get definitive answers, true data, not biased by mathematical models. In addition, it is the kind of data that previously took days to get from a laboratory and required the sacrifice of an entire, often very expensive, wafer." Often in the past, the cost of collecting such "laboratory data" exceeded the value of the data itself, even though in a sense it was "priceless" for manufacturing operations. The application of FEI's dual beam technology for IC manufacturing is rooted in a more than two-year shake out in the data storage industry. "With the data storage industry roadmap approaching and even overlapping the IC industry — we are working there with linewidths of 100nm to 200nm — manufacturers were beginning to see high aspect ratios causing yield problems; in some parts of the process, process engineers needed to know feature sizes half way down, data about sidewall angle, and a feature's position relative to buried structures," said Dawes.
 Figure 1. A high-resolution SEM image of a FIB cross section precisely placed in a group of 130nm resist lines. |
These data storage process engineers came to the conclusion that the top-down metrology information provided by their existing CD-SEM technology was not as reliable as it needed to be. With the data storage manufacturer that FEI has been working with, dual beam technology was initially brought in to calibrate existing metrology tools. "However," said Dawes, "The more that our data from dual beam was compared to tool calibrations and, more specifically, product yields, the more it showed a clear enhancement in process data quality." Now, at this manufacturer, dual beam metrology is being used full time in production and CD-SEM is being used less.
 Figure 2. A top-down SEM image of 160nm resist contacts (left) compared to a SEM image of a FIB cross section through the same group of contacts (right). |
In preparing dual beam technology for the IC industry, FEI has been working with leading IC manufacturers and equipment suppliers. According to engineers at ASML (where FEI has a development project) also reporting at the SPIE conference, lithography is at the point where you do not always know adequately what is going on in a process when you just do top-down metrology. Todd Davies of ASML told SPIE attendees, "We have used dual beam in 130nm design rule applications using KrF lithography, capturing top, middle, and bottom CD features, sidewall angles, and pitches, with both lines and contact holes at 1:1 densities. Our results show a smaller, yet more representative process window when evaluated via 3-D criteria compared to 2-D top-down techniques."
Indeed, dual beam technology is offered as a viable alternative to what may be emerging as the limits of top-down optical and CD-SEM metrologies for 130nm and beyond (Fig. 2). In a sense, it is an answer to the debate in the IC industry by some as to whether it will prove wise to extend the capabilities of top-down methods through mathematical modeling, which is the only way CD-SEM metrology will be extended.
ASML and FEI are now working on a more definitive evaluation of just how much information is missing and how much more value is added to IC manufacturing with 3-D metrology. — P.B.
Only two NGL techniques still viable
"When it comes to next-generation lithography (NGL) methods, there are only two that most people would recognize as still being on the roadmap today: extreme ultra violet (EUV) and electron projection lithography (EPL)," says George Gomba, senior manager of advanced lithography development at IBM Microelectronics (Hopewell Junction, NY). "X-ray and ion projection lithography (IPL) have been 'voted off the island', so to speak," he quipped. Gomba was the guest speaker at KLA-Tencor's lithography users forum held prior to the annual SPIE Microlithography Symposium, Santa Clara, CA. Gomba stressed that "we can't let NGL off the hook." His view is that infrastructure is the gate to enabling the remaining NGL choices and this will require advancements in electron beam writing, inspection, defect repair, and more, which could be at high cost. "NGL needs to get to alpha tools and the collection of data that follows. Remember that integration of process technology with just one of these alpha tools will only be the first fundamental step on the learning curve of how to use NGL technology to build defect-free devices. The learning curve is long ahead of us, but it must be pursued soon," Gomba concluded. — P.B.
Newly defined limit provides a key to future developments in microelectronics
Researchers at the Georgia Institute of Technology's Microelectronics Research Center have determined a fundamental limit that defines the minimum amount of energy needed to perform binary logic switching, the basic computing operation that changes a 0 to a 1 or vice-versa. Based on this limit, which depends on the single variable, absolute temperature, engineers can derive the material, device, circuit, and system limits that will determine future advances in microelectronic innovation.
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In the 1950s, electrical engineer John von Neumann first reported the fundamental limit, expressed as the equation:
E (min) = (ln2)kT
where T = absolute temperature; k = Boltzmann's constant; and ln2 = the natural log of 2. He never gave an explanation for its derivation, however.
James D. Meindl, professor of electrical and computer engineering and director of the Microelectronics Research Center, and his colleague, Jeffrey A. Davies, discovered that the limit is equal to the minimum energy required to produce a distinguishable binary transition or the minimum energy necessary for sending the resulting signal along a wire.
Meindl says that although the limit establishes a theoretical end point for electrical and computer engineers, devices will never operate close to it. Physical limits like the fact that electronic signals can't move through interconnects faster than the speed of light and quantum mechanical uncertainties would be prohibitive. More important, statistics dictate that the probability of making an error at the fundamental limit is one half, which means if a device operated just above the limit, it would be right most of the time; if it operated just below, it would be wrong most of the time.
As a result of their work, Meindl and Davis predict that engineers can expect another 10-15 years of cost-effective developments in microelectronics. "What has enabled the computer revolution so far is that the cost/function has continued to decrease," Meindl said. "It is likely that after a certain point, we will not be able to continue to increase productivity. We may no longer be able to see investment pay off in reduced cost/function."
After that, Meindl concludes, designers will turn to nanotechnology for further advances in miniaturization.
Meanwhile, he expects that although silicon will continue to be the material of choice for most IC technology, other materials will fill important niches. Meindl likened this to alternate metals — such as aluminum, zinc, and brass — replacing steel for many special functions in metalworking.
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Get the skinny on ultrathin SiN gates
Researchers have demonstrated an ultrathin gate dielectric constructed of an oxide-on-nitride stack that provides low leakage current, minimal saturation current degradation, boron penetration suppression, and improved reliability. This new technology, for use in CMOS devices at the 0.10µm node, is described in "Solutions for the 100nm node with ultrathin silicon nitride gates," on p. 75.
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Tech Briefs
Motorola Labs, San Francisco, CA, partnering with DigitalDNA Laboratories of the Semiconductor Products Sector, announced the development of magnetoresistive random access memory (MRAM). According to Sherry Garber of Semico Research Corp., MRAM has the potential to surpass current memory technologies. Preliminary data from Semico suggest that MRAM revenues totaled $48 billion in 2000.
At its Munich, Germany, wafer fab, Infineon Technologies is using silicon carbide (SiC) based technology to manufacture Schottky-diode power devices. SiC is the ideal material for high-blocking voltage power semiconductors based on its characteristics, including a higher Schottky barrier, ten times higher electrical breakdown field strength, and a thermal conductivity comparable to copper.
Numerical Technologies, San Jose, CA, has joined consortium IMEC, Leuven, Belgium, and will work toward incorporating its proprietary phase-shifting technology in IMEC's 193nm-lithography development program. Under the terms of the partnership, Numerical will provide its phase-shifting and attendant technologies as well as training and support services to IMEC and its members for a period of three years. IMEC's 193nm program involves multiple semiconductor manufacturers, capital equipment suppliers, and design companies. A new photoresist removal technology that eliminates the use of hazardous chemicals and the production of wastewater in the fabrication of ICs has been created by scientists at the US Department of Energy's Los Alamos National Laboratory (LANL) in New Mexico. This is important because an estimated 4 million gallons of wastewater are produced and thousands of gallons of corrosive hazardous materials are used on an average day of operations at a chipmaking plant. The technology, known as "SCORR," focuses on photoresist removal, where high-intensity light is combined with aggressive acids and corrosives to create ICs. The LANL photoresist removal technology produces virtually zero hazardous waste. Its closed-loop system reuses the carbon dioxide, releasing no greenhouse gases to the atmosphere. The additive co-solvents are easy to separate from the mixture, because of their low vapor pressure, and are collected and reused.
Separately, Motorola and Novellus Systems have completed a successful demonstration of Lam Research Corp.'s copper dual inlaid multilevel interconnect process. Using Lam's 300mm Teres CMP system with linear planarization technology and 300mm dielectric tech systems, contact resistance, sheet resistance, and line-to-line leakage achieved the same or better levels compared to 200mm.
Montana-based Semitool Inc. has demonstrated effective removal of post-polysilicon etch residue on wafers in work done with the European research center IMEC. Wafers are first treated with ozone and deionized water (the HydrOzone process) in a boundary-layer control technique for photoresist removal, and then, in the same chamber, with HydrOzone and diluted hydrofluoric acid (the FluorOzone process) for a pre-diffusion clean. The proprietary aqueous-based processes combine to produce an environmentally friendly wafer-cleaning technology that reduces the use of chemicals and water. The new technology can be used on several of Semitool's single-wafer, automated batch, and semi-automated batch wafer-processing tools.