Navigating yield through the maze of copper CMP defects
04/01/2001
Sumit Guha, Anantha Sethuraman, KLA-Tencor Corp., San Jose, California
Yehiel Gotkis, Rodney Kistler, Lam Research Corp., Fremont, California
Scott Steckenrider, Cabot Corp., Aurora, Illinois
overview
Many types of defects arise from the copper CMP step, and careful inspection and an understanding of the failure mechanisms allow processes to be modified to reduce the defect levels. Some of the defects that appear at copper CMP actually come from previous process steps, so the right inspection and analysis approach can improve entire process modules.
 Metrology tools, such as this KLA-Tencor eS20XP e-beam wafer inspection tool, are being used for defect identification in emerging copper processes. |
Since IBM's official announcement on copper dual damascene (CuDD) technology three years ago, the semiconductor world has been engaged in a CuDD race. However, dual damascene technology has proven more difficult to implement than initially expected. One of the reasons for this is the myriad of defects associated with Cu technology. Consequently, a significant amount of additional work with specific attention to defects is necessary to make CuDD technology production-worthy.
CMP-induced yield limiting factors
CMP is a critical operation in CuDD technology [1] because the yields are extremely sensitive to the CMP performance, and because by removing all previous layer metal deposits, CMP represents a kind of reverse processing. In this sense, it could be considered as an investigative tool, which allows one to reveal problems related to previous process steps. After the inherent process module issues are solved and an operation passes into a reasonably mature status, the next level of process integration or module interaction problems has to be resolved. The key to success here is to link the problem to its root cause, which is frequently a previous module step and hence requires more effort to discover than to correct.
 Figure 1. Copper residue detected using KLA 2135, with a) a large residue spot, and b) a small residue spot. |
Much of the defect learning in CuDD technology is erroneously a carry-over from dielectric and tungsten CMP. Even today, process defectivity is frequently quantified by running a blanket oxide film between a sequence of Cu wafers and measuring the particulate defectivity. Also, the focus of the CMP process community has often been "dishing and erosion first, and then other issues." Unfortunately, metal/dielectric loss and particulate defects are not the only yield-limiting parameters. Several other yield-limiting defects that appear at the post-CMP copper patterned wafer surface are: metallic residuals, including both Cu and barrier materials; scratching on both metal and dielectric surfaces; pin-holes and microcracks, e.g., at Cu grain boundaries, which lead to corrosion; corrosion and pitting, which affect long-term integrity of interconnects; barrier integrity damage and oxide depressions; re-deposition of by-products and fall-on particulates; and module interaction defects, in which defects introduced at previous operation steps affect later processes.
The objective of this paper is to describe the various Cu CMP-related defects that affect yield on conventional rotational platforms, and the effect of prior-level process module defects on CMP.
Nonremoved metallic residuals
Metal residues affect yield by introducing electrical short circuits. Even though copper is easier to detect because of its basic color difference from either the barrier or the dielectric, the primary challenge with copper residues is to differentiate the copper within interconnects from small excess copper spots. Figures 1a and 1b show large and small residual copper spots, respectively. (Note that for all figures presented here the full image width is approximately 50µm unless otherwise specified.)
In addition to copper, residual barrier is also frequently noted to be a yield killer. Unlike copper, however, residual barrier on top of the dielectric surface can be quite difficult to detect depending on the thickness of the dielectric. For certain oxide thicknesses, the dielectric surface may be within a dark fringe of reflected light which makes detection of residuals more difficult [2]. Residual barrier can result from insufficient polish time, due to removal nonuniformity for a "fixed time" barrier removal step, or surface nonplanarity, which can be result from recessed features at a prior level creating "barrier pools" on the next level. Such defects can be yield killers when the barrier pools are in contact with the Cu pads, as shown in Fig. 2.
Scratches
Because copper is softer than oxide or tungsten, it is scratched more easily during CMP. Common scratches in copper can be classified into three broad classes: razor scratches, chatter scratches, and skipping scratches.
Examples of these scratch classes are shown in Fig. 3. The underlying oxide, being harder than copper, can act as a scratch stopper, and prevent the scratching object from intruding too deeply beyond the field oxide level. By the time the overburden copper is removed, only the deeper sections of a former scratch will remain over the surface, so it might not look like a continuous scratch. The scratch shown in Fig. 3c might be related to copper intergranular failure along the scratch path, but the origins of each of these scratch classes have not yet been established. In addition to these three broad scratch classes, a significant number of short scratches are also seen in oxide. Scratches in copper are problematic if they replicate on the subsequent dielectric layer, because scratches in the dielectric, when followed by metal deposition and subsequently CMP, can lead to metal stringers. Similarly, deep scratches in the dielectric layer can lead to pattern distortion. A common remedy is to buff the dielectric with an oxide slurry in order to remove deep scratches.
Pin-holes and microcracks
Plated copper is a polycrystalline material, and the electrofill chemistry adds to the challenges of CMP. A typical electroplating (EP) bath chemistry is composed of CuSO4/H2SO4/DI water, accelerators (e.g., disulfides), suppressors, N2 compounds, and ppm quantities of HCl [3, 4]. The net effect of these additive-bearing baths is that the grain boundaries, especially the triple-point junctions, become more mechanically and chemically vulnerable. The CMP process generates significant shear forces on these grains, which lead to material fracturing (intergrain cracking in particular) and stress-induced chemical attack (intergrain corrosion). Examples of such grain boundary microcracks are shown in Fig. 4.
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Figure 2. Residual barrier pools created by prior-level nonplanarity. The oxide deposition replicated the recessed topography on the next level. Consequently, the barrier is recessed compared to the oxide level, which makes it difficult to remove.
In addition to the problem of additives' adsorbing and weakening the grain boundaries in the deposition step, a second source of weakness is annealing. The as-plated Cu film is nearly amorphous, and annealing, whether self-annealing or thermal, transforms the film into a crystalline structure [5]. Thermal annealing also raises the possibility of interactions between additives and copper, thereby creating surface films and weakening the inter-granular bonding. All of these contribute significantly to increased risk of crack formation at grain boundaries.
A microcrack would only trap CMP chemicals due to capillary forces. Removing residual chemicals from such microcracks completely during the post-CMP clean step may be quite difficult. Hence, any trapped chemicals will continue to propagate grain boundary damage.
 Figure 3. Copper scratch examples (detected using AIT II): a) razor scratch, b) chatter scratch, and c) skipping scratch. |
For 0.25µm technology, the number of intergrain partitions for a low Cu inclusion level could be as high as 108-109 [6]. If even one of those partitions allows corrosion to proceed down to the bottom of the line, the chip will be scrapped. This establishes the significantly higher risk of corrosion for Cu CMP technology compared to other metal films.
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Figure 4. Optical microscope image showing intergranular fracture in electroplated Cu films after CMP.
In addition to intergranular cracks created under stress, pin-holes in the as-electroplated films also increase the risk of corrosion. Such pin-holes can be seen everywhere (e.g., in the bond pads, within the Cu lines), and pin-holes can extend deep into the film. They can also trap corrosive chemistry by capillary action and corrode the film even in the absence of CMP. The origin of these pin-holes is currently unknown.
Corrosion and pitting
Figure 5 shows an example of corrosion in line structures. The occurrence may be completely random (i.e., the neighboring lines are not affected), which makes root-cause analysis and control more difficult. Although CMP slurry chemistry is frequently blamed for corrosion, the role of EP film quality cannot be neglected.
 Figure 5. An example of line corrosion in Cu CMP (defects were detected using AIT II). |
In addition to line corrosion described above, another mode of corrosion observed is "edge corrosion," which is frequently limited to multi-material interfaces such as that between the dielectric/barrier layers and the Cu fill. Any separation of the interface generates gaps that serve as traps for CMP chemicals and lead to corrosion. This type of corrosion is visually characterized by the waviness of the copper at the dielectric/barrier interface. Another form of corrosion defect popularly referred to as "mouse-bites" — a small portion of an otherwise intact line is missing — may have similar origins since mouse-bites often occur at multi-material surfaces as well. The origins of such defects are presently unknown, though.
 Figure 6. An AFM image of uncontrolled metal etch on a bond pad in Cu CMP. |
In addition to corrosion, pitting is also frequently encountered on a post-CMP wafer surface. Pitting increases with the size of the copper features, so pitting is worst in bond pads, with minimum pitting occurring with thin lines. Since grain growth and fill chemistry (additive concentration) would be different in narrow vs. wide features, it would suggest that pitting may be related to either the additive concentration or the grain size, with a larger grain size being more vulnerable to pitting.
In addition to corrosion, some CMP processes can also create conditions of uncontrolled metal etch, giving rise to an uneven copper surface. This is more pronounced over bond pad areas, as seen in Fig. 6. Since the as-deposited films typically have a texture that evolves with annealing, metal etch problems could be related either to the slurry or specific textures that generate conditions of differential etch rates over multiple grains [7].
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Figure 7. Incomplete barrier removal showing pits in the barrier that extend to the oxide.
Barrier integrity damage and oxide depressions
Barrier integrity damage and oxide depressions appear mostly as the result of EP/CMP or CMP/barrier deposition interactions. Depressions over the post-CMP dielectric surface are detected during post-CMP wafer inspection (Fig. 7). The depth of the depressions (350-600») normally exceeds the barrier layer thickness. Examination of the barrier surface at different stages of its removal show the depressions to be caused by oxide over-polishing through perforations appearing in the barrier layer in the early stages of its removal. Deep pits in the dielectric surface may present the same problems discussed earlier with scratches.
Re-deposition of by-products and fall-on particulates
During defect detection and classification, deposition by-products are frequently not differentiated from particles since their impact on yield is similar. More detailed differentiation of slurry/by-product residues from small particles requires more detailed (and slower) review, typically by SEM or AFM. Residues or particles from one CMP step may generate subsequent film defects. Such a particle may be dislodged during subsequent processing, such as an oxide etch step, which may alter critical dimensions and possibly lead to die failure by any of several mechanisms.
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Module interaction defects
In some cases, post-CMP defect detection and classification can reveal previously undetected defects that are unrelated to the CMP process step. Incomplete patterning (caused by errors in either lithography or etch steps) can be uncovered in the CMP step and may be interpreted as extreme over-polish. Possible causes of such defects could range from a dirty litho mask to a faulty ash step (resist patterning step) that might shield a region from etch. Post-CMP defect review, by AFM for example, can be used to differentiate between CMP defects and defects from previous steps, thus obtaining feedback for improvement in other process steps as well as CMP.
Another example of module interaction defects would be random EP film thickness nonuniformity ('swirls') that cannot be captured by conventional polar map measurements using four-point probes. Figure 8a is a collection of four images from four perpendicular points on a wafer; the images are arranged clockwise from top left and the wafer rotation direction is drawn on the images. Figures 8b and c show the microstructure of the swirls, which shows that the grain size within the swirls is different from the surrounding regions. Since Cu CMP performance is primarily dictated by plated film thickness range, such swirls introduce risk of residual Cu, which may be undetected by the end-point systems before the wafer passes to the barrier removal phase. In the event that the barrier is removed while Cu is still present on the surface, the wafer will have to be scrapped.
Discussion
Navigating process technology through this maze of defects is a challenge to any process engineer. Further, the number of defects in CuDD technology is orders of magnitude higher compared to previous-generation technology. Clearly, best practice solutions are required at the OEM level that would focus on defect issues in addition to dishing and erosion.
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Metal residuals present the largest challenge with respect to yield. EP film defects such as swirls increase the risk of metal residuals. Although detection of Cu residuals is fairly simple conceptually, designing processes — especially end-point systems — to detect Cu residuals is a significant challenge. Most end-point systems are not equipped to look for such minute detail, so one has to compensate by over-polishing the wafer at the expense of dishing and erosion. One way to control the risk of metal residuals would be to monitor the worst-case range of EP films (including swirls) by inspecting the whole wafer instead of using only 49-point measurements. One suggested method is to use bright-field imaging, such as Surfscan SP1TBI. Figure 9 shows an electroplated Cu wafer where the swirl marks are detected by the bright-field channel of SP1TBI using DIC contrast. By consistently monitoring EP wafers and feeding forward the information to Cu CMP, one may decrease the risk of metal residuals.
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Figure 9. a) A bright-field map of an EP Cu wafer with swirl marks, and b) a magnified view of a swirl mark captured by SP1TBI using DIC, showing a 2µm step height.
In addition, module specifications need to accommodate a higher level of over-polish. Unfortunately, commercial copper slurries today do not provide a wide enough process window. New slurries with higher Cu-to-barrier selectivities (~100:1) need to be developed. Alternatively, different integration strategies need to be investigated. Candidates include use of a thicker dielectric deposit than target and finally buffing of the excess dielectric, or use of a thicker barrier deposit (350-400» instead of the conventional 150-200»). Thus, the problem of Cu residuals is primarily a process challenge.
Since the barrier can be removed without affecting dishing and erosion (with Cabot EPC-4200, for example), any barrier residuals present less of a process challenge. However, since any barrier present will short the active regions just like copper, and because such failure can be detected only at the parametric test step for any interconnect level, thereby reducing throughput, barrier detection is a metrology challenge. New approaches to detecting residual barrier that are independent of dielectric thickness are necessary.
After metal residuals, scratches represent the next most important class of yield killers. The following objects are potential sources of scratching for Cu and dielectrics: large particles or agglomerates in CMP slurry; tool debris (delaminated diamonds from pad conditioner); pad-generated material (debris, conditioning-created features, groove edges, etc.); and solid process by-products accumulated over the pad surface, causing shallow "chemical" scratching (CuO + Cu -> Cu2O).
The following are some common sense best-practice solutions to controlling scratches: minimize accumulation of process by-products over the pad surface by proper pad conditioning and cleaning; avoid excessive pad grooving and scratching due to conditioning; and prevent flake formation during barrier removal phase by use of pseudo-mechanical and not barrier-aggressive slurries for barrier removal.
Material removal in Cu CMP results in: 1) accumulation of by-products and debris in pad pores and grooves, 2) absorption of chemicals by pad material, 3) pad staining and pore glazing due to heating of the pad material, and 4) direct erosion of pad material. All of these cause deterioration in scratching performance. "Normalized removal work" (NRW), the amount of material removed by a unit of active pad area, is a good parameter to characterize performance potential for a given CMP technique. A lower NRW is considered to be better for CMP. A low NRW technique (e.g., a linear belt approach) combined with balanced conditioning prevents formation of large by-product residues, minimizing shallow "chemical" scratching. Other sources of large agglomerates are the slurries themselves. Better cooperation is needed between OEMs to simplify slurry delivery paths, thereby avoiding the possibility of old slurry residues in the delivery lines contributing to large particle counts.
Controlling the source of scratches, better depth differentiation of scratches, and better yield correlation algorithms are all needed to separate the "killer" scratches from the "nuisance" class.
The third most important class of defects is corrosion. Wafers that may pass defect inspection in a post-CMP state can continue to corrode, with the corrosion manifesting itself at a later stage. Since CMP utilizes a combined chemical/mechanical action to remove the material, the interconnects are exposed to corrosive conditions by the chemical component of the process. One way to control corrosion is to choose a slurry with a static corrosion rate much less than the CMP removal rate, which makes the material removal surface propagate faster than corrosion, helping to eliminate corrosion effects. Further, instead of using inhibitors in the slurry itself, flushing out the slurry and applying inhibiting solutions during the post-CMP clean step should be considered.
Pin-holes, microcracks, and intergrain boundaries are more susceptible to corrosion. Thus, one way to control corrosion may simply be to re-visit the self-annealing vs. thermal annealing of electroplated wafers. The film annealing was designed to counter the inherent center vs. edge difference in CMP removal rate for EP films. With the advent of modern multizone carriers that can compensate for differences in removal rate in different sections of the wafer, the requirement to "stabilize" the film prior to CMP needs to be revisited. Perhaps it would be reasonable to carry out the CMP step in the as-plated amorphous state of the Cu film, since amorphous films have been known to exhibit excellent corrosion resistance, followed by an anneal step to crystallize the film. Of course, this would represent a departure from the conventional thinking by designing processes with the approach of "defects first, dishing and erosion later."
Conclusion
This paper discussed the major defect classes seen in dual damascene copper CMP technology, with an emphasis on defects that affect yield. The three important defect classes considered critical to yield are metal residuals, scratches, and corrosion. Cu CMP performance is affected by distribution of Cu properties in both macro- and micro-scale for all three layers removed (barrier, seed Cu, and bulk Cu). Interaction with previous process steps requires operation consistency across the whole back-end block. Extensive integration work still has to be done to tune design rules, deposition, annealing, and CMP to optimize the whole back-end cluster.
Acknowledgments
The authors wish to thank Rick Foster of Cabot Corp. for his support and commitment to this program.
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