Solutions for the 100nm node with ultrathin silicon nitride gates
04/01/2001
Sagy Levy, Robin Bloom, James Lam, Avishai Kepten, Mattson Thermal Products Inc., San Jose, California
overview
To continue the scaling trend of CMOS technology, the anticipated high gate leakage current in ultrathin gate dielectrics must be suppressed. In addition, dielectrics must also suppress boron diffusion and act as a barrier. A stack of oxide and nitride layers is an attractive replacement for the gate dielectric. In this article, we present a gate dielectric composed of an oxide-on-nitride stack that provides two orders of magnitude lower leakage current than thermal oxide, minimal saturation current degradation, boron penetration suppression, and improved reliability. Good wafer-to-wafer repeatability is demonstrated over a period of a few months.
 Figure 1. LPCVD system used for ultrathin silicon nitride gate dielectrics. |
The International Technology Roadmap for Semiconductors (ITRS 1999) [1] predicts for the 0.10µm technology node that the gate oxide thickness must be approximately 14». Thinning the gate dielectric has been instrumental in controlling short channel effects as MOS gate dimensions are scaled down. For the last two decades, the gate oxide thickness was scaled down linearly with the channel dimensions. The shrinking of CMOS devices has increased the demand for gate dielectrics with a higher dielectric constant than silicon dioxide. This was necessary to reach ultrathin (<15») equivalent oxide thickness (EOT) without compromising the gate leakage current. In addition, PMOS transistors require the gate dielectric to suppress boron penetration. In order to meet the requirements of next-generation CMOS devices, the gate dielectric should exhibit saturation current levels comparable to thermal oxide film of the same electrical thickness. Another important issue when using a new film for the gate dielectric is reliability. The reliability can be measured with lifetime projection and the charge to breakdown (Qbd) derived in constant current stressing.
The addition of a nitride layer to the oxide allows the increase of the physical dielectric thickness while maintaining the same equivalent oxide thickness. The use of CVD nitride provides lower leakage current, reduced boron penetration, and immunity from hot electron carriers.
Lamp-based LPCVD cluster tool
The SiN/SiO stack was processed on an LPCVD (low-pressure chemical vapor deposition) system at Mattson. The surface preparation module has the capability of UVCl2 (UV-activated chlorine species) and HF-Me (vapor HF with methanol). The UVCl2 can be used to remove metal contamination; the HF-Me is used for native oxide removal. All of the cleans can be used for surface preparation in the integrated high-vacuum processing just prior to the deposition step (Fig. 1).
The LPCVD chambers are cold wall reactors with tungsten halogen lamp-based heating and high vacuum. The wafer temperature is monitored by an emissivity-enhanced system, and the effective emissivity range is 0.20-0.95. Precise, closed-loop control, combined with short residence times and high-vacuum capability, allows the growth of ultrathin films with good repeatability, uniformity, and compositional control. These system characteristics are essential to achieve gate dielectric processes for the 0.10µm generation.
Experimental setup
NMOS capacitors were fabricated on p-type epi-silicon wafers using LOCOS isolation. PMOS capacitors were fabricated to verify the boron penetration suppression.
First, the wafers were oxidized in the LPCVD chamber in an NO ambient. Then, silicon nitride was deposited with NH3 and SiH4. After the CVD nitride deposition, the samples were annealed in an NH3 ambient, followed by an N2O ambient. The Si3N4-SiO2 stack was deposited and annealed following the method suggested by Kwong [2]. In this process, a base oxide is formed by oxidizing the silicon substrate in a NO atmosphere, and this step is followed by the CVD nitride (Si3N4) deposition. The following two steps are annealing in NH3 and then annealing in N2O ambient in order to get rid of defects.
To characterize the saturation current, the carrier mobility, and other electrical parameters, transistor structures were fabricated. The EOT was extracted from C-V curves using a simulation program, which includes quantum mechanical and poly depletion effects. The leakage current is taken at accumulation, which was -1.5V for NMOS transistors. I-V and C-V measurements were combined to create the current leakage versus EOT curves.
Results and discussion
The dielectric constant of the film was examined by looking at the ratio between physical (Fig. 2a) and electrical thickness (Fig. 2b). The resulting dielectric constant for this example was 5.8. The process repeatability of 16.3» EOT over five months can be seen in Fig. 2b. EOT repeatability suggests that the physical thickness and nitrogen content of the film are repeatable.
 Figure 3. The reaction mechanisms are reflected in a) an Arrhenius plot of the CVD step, and b) the activation energy as a function of deposition temperature. |
Deposition uniformity was optimized by tuning the five-zone axisymmetric heater control. A typical 49-point line scan can be used. Since the refractive index is an unknown, an ellipsometric measurement is not an absolute measurement but a relative one. (The absolute thickness can be measured by transmission electron microscopy [TEM].) The refractive index of the material is not available because it is an alloy of three elements (silicon, oxygen, and nitrogen). The purpose of the line scan is to test the uniformity, which is a site-to-site relative measurement. The uniformity achieved on an 8-inch wafer that was tested is 1s = 1.23%.
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Figure 4. Process temperatures have an effect on film quality, as shown by a) the CVD temperature effect on leakage current, and b) the effect of N2O and NH3 temperature on leakage currents.
Various process steps were studied in order to determine the sensitivity of the film parameters to the different process steps. First, the CVD step was examined. Deposition rate dependency on the deposition temperature was studied in detail. As part of this study, Arrhenius plots of the CVD step were generated (Fig. 3a).
The activation energy was extracted from figures similar to Fig. 3a. In Fig. 3b, the activation energy is plotted over a wide temperature range. As can be seen, the activation energy is not constant with respect to the temperature, suggesting that the deposition mechanism changes over this temperature range. In the low-temperature range, surface reaction is the dominant mechanism. Therefore, the activation energy is typical for surface reactions. However, in a higher-temperature range, the typical activation energy value is higher, representing the summation of various processes that are dominant at higher temperatures (material transport to the surface, surface desorption, and surface reaction).
The exponential dependence of the reaction rate will have some effect on process stability and uniformity. Decreasing the temperature will result in decreasing the temperature sensitivity. This implies that the lower the deposition temperature, the better the uniformity is across the wafer and the uniformity from wafer to wafer. Because the films are so thin, high deposition rates are not an important issue for throughput consideration.
Deposition rate
The CVD step was further studied, and the sensitivity of the deposition rate to mixing ratio was examined. The sensitivity of the deposition rate as a process parameter is defined as the derivative of the deposition rate with respect to the examined process parameter. It was shown that lowering the mixing ratio resulted in a more sensitive deposition rate.
From these results, it is highly recommended that a high mixing ratio be used to achieve low sensitivity. Furthermore, the electrical results suggest that the quality of the film is better when using high mixing ratios. The dependency of the deposition rate on the mixing ratio is explained by the reaction mechanism of the silicon nitride deposition.
There are two competing reactions that occur when SiH4 and ammonia are introduced to the reaction chamber:
- 3SiH4 + 4NH3 -> Si3N4 + 12H2
- SiH4 -> Si + 2H2
The polysilicon deposition rate (reaction 2) is greater than the silicon nitride deposition rate. By introducing an excess of ammonia to the reaction chamber, the silane will be mostly consumed by the ammonia in reaction 1, and therefore, will eliminate the second reaction. This explanation was checked thermodynamically but was not confirmed by a kinetic model. The phenomena may be explained by reaction-dynamic considerations [3].
Leakage current
Using capacitor structures, we generated a leakage current dependent on various process parameters. The leakage current is shown in a normalized form. The normalization is done by comparing the measured leakage current to a nitride master plot and interpolating the relevant thickness. The nitride master plot points were pre-qualified to exhibit a low defect density and high dielectric constant. The CVD temperature effect on normalized leakage current can be seen in Fig. 4a. As the CVD temperature decreases from 800°C to 750°C, the normalized leakage current decreases.
The NH3 and N2O anneals have a very important role in reducing the leakage current, as seen in Fig. 4b. Increasing the N2O temperature or NH3 temperature will result in a reduction of the normalized leakage current.
The current conduction mechanism in silicon nitride is well established [4-6]. A silicon nitride sample that has not been subjected to annealing has a typical defect-assisted current conduction mechanism. The current conduction is dominated by electrons jumping between geometrically close defects, a mechanism described by the Frenkel-Poole equation. If the gate leakage current is plotted versus the square root of the electric field, a straight line will result if the conduction mechanism obeys Frenkel-Poole. When silicon nitride films are subjected to the proper annealing, the current conduction mechanism can be altered from Frenkel-Poole to Fowler-Nordheim [2]. The deposition step is also a critical factor in determining if the resulting film will exhibit a Frenkel-Poole or a Fowler-Nordheim current conduction mechanism [7]. To check if a gate nitride dielectric obeys the Fowler-Nordheim current conduction mechanism, log(Ig/E2) should be plotted versus 1/E. If this plot yields a straight line, then it is concluded that the film exhibits a Fowler-Nordheim current conduction mechanism and that it has a very low defect density, as can be seen in the equation:
Ig = Area*A*E2*e(-B/E)
where:
Ig = the gate leakage current;
Area = the gate dielectric area;
A, B = constants that includes the barrier height and the electron effective mass; and
E = the vertical electrical field in the gate dielectric.
By optimizing the annealing steps, we have achieved a film that exhibits the Fowler-Nordheim current conduction mechanism.
Process optimization
To achieve a nitride dielectric film with low defect density, one has to apply extensive annealing steps and to optimize the nitride deposition step. As described above, part of the essential annealing process includes introducing oxygen to the film. This in turn will reduce the defect density in the film. However, introducing oxygen to the film will decrease the dielectric constant [8]. If the dielectric constant is reduced significantly, the physical thickness will be reduced and the resulting direct tunneling current and Fowler-Nordheim current will be increased.
 Figure 6. Boron penetration study. |
It is therefore a matter of optimization and balancing the annealing condition to anneal most of the defects in the film. It is important, however, not to exceed a limit where the dielectric constant is reduced significantly. This optimization was performed by adjusting the N2O annealing temperature to the deposited nitride CVD thickness. An example of such an optimization process can be seen in Fig. 5a. As discussed above, only the correct ratio between CVD-deposited film thickness and N2O-annealing temperature will yield low leakage current ratio. Another important factor in the silicon nitride deposition is the defect level in the deposited film. It was found that films grown in lower temperatures yielded lower leakage currents, as can be seen accordingly in Fig. 5a.
Using these trends, the films were optimized to achieve an EOT of 14.5» and leakage current close to two orders of magnitude better than thermal oxide, as seen in Fig. 5b.
 Figure 7. Carrier mobility before and after optimization. |
A boron penetration study was conducted on PMOS devices with a P+ ion-implanted polysilicon gate. The polysilicon gate was implanted with BF2 ions, and the gate was annealed with different drive-in conditions in a rapid thermal annealing system. To see if the nitride-on-oxide stack serves as a boron diffusion barrier, the flat band voltage was examined for the difference between the work function of the polysilicon gate and the substrate. Diffusion of the boron from the polysilicon to the substrate will alter the work-function differences and will result in a significant flat band voltage shift. Figure 6 shows the flat band voltage of P+ boron gate capacitors, with different annealing conditions resulting in the same flat-band voltage shift. The EOT and leakage current will also change with boron penetration, but as can be seen in Fig. 6, the change in EOT and leakage is minor and does not correlate to the process conditions.
Having high saturation current is another requirement for the gate dielectric for next-generation devices. In order to quantify this parameter, the drain current was normalized to carrier mobility and was compared to the thermal oxide mobility. After optimizing the Si/SiO2 interface, the carrier mobility in the range of the "on state" voltage of the transistor was examined. The carrier mobility reaches values near thermal oxide (Fig. 7). The operating voltage for the 0.10µm generation is approximately 1.2-1.5V, which translates to an electric field of 1.15-1.2MV/cm. In this range, the mobilities of oxide and nitride have similar values.
Conclusion
Silicon nitride gate dielectric was deposited and annealed with encouraging results. Production feasibility — i.e., low leakage current, boron penetration suppression, and thermal oxide values for carrier mobility — was demonstrated. The leakage current of the CVD nitride is two orders of magnitude lower than thermal oxide leakage current with an EOT of 14.5». Boron penetration was completely suppressed by the nitride on the oxide film. Mobility was optimized to achieve the values of thermal oxide, thereby yielding the saturation current of thermal oxide.
Acknowledgments
The authors would like to thank Hedvi Spielberg and Eli Iskevitch from Mattson for helping with the project; and Dim Lee Kwong from the University of Texas, Austin, for performing the electrical measurements. North Carolina State University created the program used to simulate the EOT.
References
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Sagy C. Levy received his BS in chemical engineering and MS in heat transfer and crystal growth simulation from the TECHNION (Israel Institute of Technology). He has more than five years' experience as a senior process engineer at Mattson Technology, working on HSG for capacitors and advanced gate dielectrics.
Robin S. Bloom received her BS in chemical engineering from Pennsylvania State University. Her post-graduate work was in material science and engineering at Lehigh University. She has more than 20 years of experience in the semiconductor industry at AT&T, Honeywell, United Technologies, Tegal, and Genus.
James Lam received his BS in engineering physics from the University of California, Berkeley. He has worked in the semiconductor industry for more than seven years, primarily on CVD equipment.
Avishai Kepten received his PhD in electrical engineering from the TECHNION. He has more than 20 years of experience in the semiconductor industry at MCNC, SCD, Tower Semiconductors, and AG Associates.
For more information, contact Donald Yoshikawa, Mattson Technology, 2800 Bayview Drive, Fremont, CA 94538; ph 408/935-2825, fax 408/935-2715, e-mail [email protected].