Electrochemically deposited solder bumps for wafer-level packaging
04/01/2001
Gary Solomon, Semitool, Kalispell, Montana
overview
The semiconductor industry is adopting wafer-level packaging as it continues to be driven by economic and advanced technology issues. State-of-the-art packaging requires the ability to deposit fine pitch solder bumps with excellent process control. This article discusses the growing need for solder bumps and the challenges of the technology involved in controlling their deposition.
 Figure 1. Area array of 250µm pitch reflowed solder bumps provides flexibility. |
As semiconductor manufacturers continue to shrink on-chip features, the need to make contact to those reduced size features becomes a more significant constraint. The increased density of inputs and outputs (I/Os) on chips has driven the pitch of peripheral pads down to the 70µm range. Peripheral pads at this density remain within the capability of wire bonding tools. As the I/O density increases for some devices, though, wire bonding technology will be unable to deliver the required mechanical and electrical package performance to maintain signal integrity. Wafer-level packaging solves this problem by providing a way to make electrical connections to the chip above the active circuitry, rather than only along the periphery of the chip.
Solder bump arrays
Once the entire area of the chip becomes available for the package interconnections, some flexibility is possible with the layout of the solder bumps. With high I/O counts, area arrays would be used. As the I/O count is lowered, arrays with some bump locations removed (or "depopulated") are employed, leaving the center region with fewer or no bumps. Rows of bumps along the periphery of the chip can also be deleted. Figure 1 shows an area array of 250µm pitch solder bumps. The base diameter of each solder bump is 125µm.
 Figure 2. Square chip size based on I/O pad count. |
On complex chips with high I/O counts, the density of I/Os — rather than the circuit size — may determine chip size. Figure 2 shows how a square chip size varies as a function of the I/O count for both perimeter pads and area arrays. For area arrays, the chip size increases much more moderately as a function of I/O count.
Terminology
Some effort is required to avoid confusion with the terms used for wafer-level packaging:
- Wafer-level packaging (WLP) produces a chip/die/device that is ready for direct assembly onto the final substrate or final system platform.
- A "bumped chip" refers to a chip that has solder bump interconnects but still receives additional packaging after becoming singulated (by wafer dicing — sawing apart the chips on the wafer).
- Wafer-level processing produces both WLP chips and bumped chips.
- A wafer-level package is the same size as the chip, since the package is completed in wafer form and becomes ready for final assembly upon singulation.
- A chip scale package (CSP) is the result of packaging a bumped chip, and is only slightly larger than the chip size when it is in wafer form.
Redistribution
Nearly all chips are currently manufactured with peripheral bonding pads. Wafer-level packaging schemes use a technique known as redistribution to connect the peripheral pads to an area array of solder bumps on the surface of the wafer (Fig. 3).
There are at least three methods of creating the solder bumps:
1) application of preformed solder balls,
2) screen printing, and
3) electrochemical deposition (electroplating).
Preformed solder balls are typically used for pad pitches greater than 700µm. Screen printing can be used for pitches down to the 200µm range. Electrochemical deposition makes it possible to deposit the bumps at any pitch that can be imaged by photolithography, so it appears to be more readily scalable to smaller bumps and higher bump densities than competing techniques.
 Figure 3. Peripheral bonding pads redistributed to an area array of solder bumps; inset: redistribution traces and under-bump pads. (Source: Fraunhofer IZM) |
The basic sequence of wafer-level packaging with redistribution and electroplated solder bumps is shown in Fig. 4. Another level of interconnect is created that defines an under-bump pad that is connected to the peripheral bonding pad. The under-bump pad is exposed by a via in a dielectric layer. Then the entire wafer receives an under-bump metallurgy (UBM) stack that provides an electroplating seed layer on top of a diffusion barrier and adhesion layer. The plating mask is formed in photoresist that may be 25-100µm thick. The solder bump is electroplated within the via in the case when a thicker photoresist is used. The solder bump is typically electroplated above the photoresist when it is <50µm thick (overplating or mushroom plating). The photoresist is then stripped and the UBM is etched away everywhere it is not covered by the solder bumps. Figure 5 shows a SEM micrograph of an "as-plated" solder mushroom bump at this phase of the process. Finally, the bumps are reflowed, causing them to reform in the shape of truncated spheres (Fig. 1).
Producing high-performance solder bumps by electroplating
Electroplated solder bumps are produced by passing current through a full (wafer area) coverage seed layer, from the entire circumference of the outer edge of the wafer, through the vias in the photoresist mask. Figure 6 shows how this is accomplished in a single-wafer fountain plating system. The automated handling system places the wafer in a plating head that clamps the wafer in a ring contact assembly. The photoresist has an edge bead removal region, EBR, around the outside edge of the wafer, which exposes a ring of seed layer metal. The ring contact assembly makes electrical contact to this exposed seed layer around the full circumference of the wafer. This ensures optimal plating current uniformity.
 Figure 4. Process flow for redistribution and electrochemically deposited solder bumps. |
The ring assembly also isolates this electrical contact region from the electrolyte by placing a circular, elastomeric seal against the photoresist, just inboard of the EBR. When the contact is not isolated from the electrolyte, that region around the edge of the wafer also plates with solder ("edge plating"), which negatively impacts the bump height uniformity across the wafer. The plating head lowers the wafer, front side down, to contact the meniscus of the solder electrolyte, which is flowing up and over the edge of the plating cup (i.e., "fountain plating").
 Figure 5. "As-plated" solder mushroom bump after photoresist strip. |
The wafer is rotated during the plating cycle to eliminate any other source of localized non-uniformities in the plating cell. Wafer rotation also allows control of the boundary layer, which is a factor in the plating rate. The other terminal in the plating cell is a consumable solder anode, with the same alloy composition as the electrolyte and target solder bump composition. This enables excellent plating bath composition control for high-volume manufacturing. The replacement of the metals in the electrolyte from the same composition anode provides long-term stability of metals in the electrolyte. The current density across the wafer surface is controlled by shaping the electric field and controlling the electrolyte's flow path in the plating cell.
The key parameters that determine solder bump yield are: the uniformity of bump height across the die ("co-planarity"); the uniformity of bump height across the wafer; and the uniformity of composition of the solder alloy, both within an individual solder bump and also among all of the bumps.
All of these aspects of the solder bump uniformity may be degraded by problems with the properties of the seed layer, electrical contact to the seed layer, leakage past the seal allowing "edge plating" around the outside edge of the wafer, and irregularities in the symmetry of the electric field within the plating cell.
Co-planarity, or within die uniformity, is mainly a function of bump layout in the photoresist pattern and is not significantly affected by a well-controlled plating cell. The co-planarity specifications are most important and essentially rely on the tallest and shortest bumps within a die or chip to be within a specified range for the final assembly connections to be reliably made. Careful consideration of the bump layout design within the die pays large dividends in the ultimate reliability of the assembled part.
 Figure 6. Cutaway view of a single wafer fountain plating system. |
Across wafer or within wafer (WIW) uniformity is the primary measure of the performance of a plating cell. The components that allow adjustment of the electric field within the plating system control this parameter. Mask design also plays an important role since we are plating a rectangular array of die in a radially symmetric system. Full wafer mask aligners are preferred over steppers for this application because the regions around the edge of the wafer may be patterned with "dummy" bumps to provide more uniform current density through the plating mask. They also allow a photolithographic EBR process that may be more tightly controlled than solvent stripping techniques.
Uniform composition of the solder alloy enables consistent reflow behavior. The composition of the solder alloy depends, in part, on the plating rate, which is a function of current density. Also, the composition of the consumable anode and control of the plating bath — electrolyte — are key to delivering a consistent and on-target solder bump composition. Low alpha particle emissions are obtainable by providing "low alpha lead" in the anode and the electrolyte. All other aspects of the plating process remain unchanged.
Lead-free solder alloy compositions for solder bumping are trending toward tin/silver/copper. Tin/silver electroplating components are available and being characterized and used.
Electroplating this ternary solder alloy presents many interesting challenges especially in the "near eutectic" composition.
 Figure 7. Plating area within a tapered via and above the photoresist. |
When the solder bump is reflowed, it is heated to the point that it becomes liquid and, due to surface tension, reforms into a sphere on top of the available wettable metal base. The reflowed bump height is dependent on the area of the wettable under-bump metal pad and the volume of the electroplated solder. The area of the under-bump pad will vary with control of the photoresist pattern processing and the UBM etch undercut of the plated solder bump. The volume of the plated bump will vary with the photoresist dimensions of the base of the via, the taper of the sidewalls of the via, and the height of the photoresist. Clearly, process control of the plating mask patterning is very important. Additionally, when solder is plated above the height of the photoresist (overplating) it expands in the shape of a mushroom and is sometimes termed "mushroom plating."
If the uniformity of the plating rate is not well controlled, variations in the mushroom bump height will occur, leading to different volumes and non-uniform reflowed bump heights. This is one of the reasons a photoresist thickness on the order of 100µm is used so that the required volume of plated solder is achieved without mushroom plating.
Bump height uniformity is also a function of solder deposition rate. At higher deposition rates, the bump height uniformity worsens. The degradation of WIW bump height uniformity with increased plating rate is thought to be due to a "magnification" of variations of plating rates across the wafer. The details of the mechanism are not well understood.
With tapered vias, if the electroplating current is held constant, the current density will drop continuously because the available area for plating increases continuously; it increases slowly as the tapered via fills, then increases dramatically as the mushroom begins to form (Fig. 7). For that reason, the electroplating process requires an algorithm to increase the current as the plating area increases in order to maintain constant plating current density and uniform composition throughout the height of the solder bump. An alternative approach is to maintain a constant plating voltage and allow the current to increase as the plating area increases, thereby maintaining a constant current density and, therefore, a stable plating rate.
In a standard production fountain plating module, solder bumps have been shown to achieve co-planarity of ±4µm, uniformity of bump height across the whole wafer of <8%, and composition control of ±1% by weight. (Across wafer bump height uniformity is expressed as the 3s value of the individual bump heights divided by the mean, expressed as a percentage.) These are "as-plated" values for 70µm tall high-lead (95% Pb) solder bumps plated at 4µm/minute, and for eutectic solder (63% Sn) bumps plated at 2µm/minute. The uniformity values typically improve after reflow. (Electroplated solder bumps increase in bump height when reflowed, so, if the distribution of bump heights remained constant, the increased mean value would decrease the calculated uniformity.)
In a state-of-the-art fountain plating module, these uniformity values have been cut in half, while maintaining the composition control. Development projects are underway to increase the plating rates while maintaining the uniformity performance.
Advantages of wafer-level packaging
Wafer-level packaging based on redistribution is already delivering cost advantages to many wafer fabs worldwide. All of the processing steps may use existing frontend technology for deposition, lithography, etch, and electroplating. At this point, it is possible to complete a significant amount (if not all) of the electrical testing before dicing the wafer.
Wafer-level processing offers economic advantages because it is less costly to package and test each chip before dicing the wafer. Test system capability is close to enabling full speed, functional testing on wafer-level packaged die. Since wafer-level packaging occurs in the fab, the semiconductor manufacturer saves the time and cost associated with shipping the wafer to a packaging plant. Quicker access to test results increases revenue by tightening the manufacturing feedback loop: The fab gains performance and yield information sooner and therefore may tune the process to improve yield in a much more timely manner. Less WIP is at risk with this manufacturing concept.
Wafer-level packaging also cuts costs by moving the packaging upstream to the "frontend" of the process. Frontend wafer manufacturing costs remain nearly constant when IC manufacturers increase the number of chips/wafer, either by increasing the size of the wafer or decreasing the size of the chips. However, traditional backend packaging costs increase linearly with the number of chips on the wafer since many steps must handle individual chips. When wafer-level packaging process steps occur in the frontend, they deliver the cost advantage characteristic of ICs. The packaging cost/chip goes down as the number of chips on the wafer goes up.
Wafer-level processing is evolving to where semiconductor manufacturers can fabricate all the packaging and complete all device testing on the wafer, so that a newly diced chip is ready for direct attachment to the final system platform. As the industry approaches this goal, electroplating of solder bumps will remain a key enabling technology for wafer-level packaging because it can economically achieve the highest integration density with high reliability.
Conclusion
Wafer-level packaging continues to gain momentum as a viable packaging approach. A key advantage of WLP is that a whole wafer is processed simultaneously, instead of the sequential processing typical of traditional back-end tools that process singulated chips. The creation of uniform bumps on a wafer for WLP is critical as performance and dimensional requirements increase. Electrochemical deposition of solder bumps is one approach to this, and some of the associated process challenges are addressed here.
Gary Solomon performed his undergraduate and graduate studies in physics at Montana State University in Bozeman. He has 15 years of experience in IC process development, integration, and manufacturing at National Semiconductor and Hewlett Packard. He has also held technical and management positions in the Thermal Products Division and the Electrochemical Deposition Division, and is currently the technical integration manager of the Advanced Packaging Division at Semitool Inc., 655 West Reserve Drive, Kalispell, Montana 59901; ph 406/758-7586, fax 406/257-2356, email [email protected].