248nm and 193nm lithography for damascene patterning
04/01/2001
SPECIAL SECTION: EUROPEAN TECHNOLOGY
Mireille Maenhoudt, Ivan Pollentier, Vincent Wiaux, Diziana Vangoidsenhoven, Kurt Ronse, IMEC, Leuven, Belgium
overview
A bi-layer 248nm photoresist system has clear advantages for dual damascene processes, particularly for solving planarization and dry etch resistance issues, without giving up lithographic performance. Work at IMEC has proven the capabilities of this process for 180nm technology. A similar system is available for 193nm lithography, and IMEC engineers expect similar results can be achieved soon for 130nm and even 100nm technology.
With the application of copper low-k dual damascene integration, lithography and etch become more difficult because of the complex layer stack (Fig. 1a) and intermediate topography. Moreover, the great variety of current low-k materials often requires different approaches in patterning (i.e., either "via-first" or "metal-first"). At IMEC, we have studied lithography and patterning challenges associated with different integration strategies:
- With the "full via-first at the trench level" process sequence (Fig. 1b), via lithography is done first on top of the full dual stack. Here, a key issue for photoresist is via etch resistance, because etching is done down to the bottom hardmask. The subsequent metal-trench photolithography step is challenging because it is done on severe via topography. Depending on the bottom hardmask, the bottom of the via needs to be protected with organic material during the metal trench etch. After the trench etch and strip, the dual damascene structure is filled with copper (Cu) and planarized by chemical mechanical planarization (CMP). Misalignment insensitivity is one of the main advantages of this sequence; even when the trench overlaps differently at both sides, the critical dimension (CD) of both via and metal is within specification.
- The "partial via-first at trench level" (Fig. 1c) is similar to that just discussed except that the via etch is done partially. In this case the bottom of the via has to be fully cleared, making the subsequent metal trench etching easier. However, this approach is misalignment sensitive; in case of misalignment or, more specifically, in case of reverse overlap to the via at both sides of the trench, the final CD of the via will be smaller than designed. This can lead to filling problems and thence to yield loss.
- With the "full metal-first at trench level" (Fig. 1d) the metal trench level is patterned before the via level. Trench lithography is done on top of the dual damascene stack where a top hardmask is optional. The trenches are etched down to the middle of the stack and resist is stripped. The second via photolithography step is again much more challenging because of topography variations that are even more severe than in the via-first approach, since a variety of trench linewidths and pitches is possible. After via etch and strip, the dual damascene can be filled with Cu. When this process involves tuning the via etch process, dual damascene patterning can be alignment insensitive.
- The "partial metal-first at trench level" approach (Fig. 1e) is very similar to the approach above except that a more complex stack is used with a single or dual top hard mask. In the metal trench etch, only the top hardmask is etched. This leads to less severe topography for the subsequent via photolithography step. The integration is, however, misalignment sensitive if the via-etch is selective to the top hardmask.
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Figure 1. a) Typical layer sequence in a low-k dual damascene stack. Processing sequences in b) full via-first at trench level, c) partial via-first at trench level, d) full metal-first at trench level, and e) partial metal-first at trench level sequences.
We have checked the initial feasibility of patterning dual damascene using conventional single-layer resists in combination with and without an organic bottom antireflection coating (BARC). Using these resist systems, we encountered various issues. While the following discussion deals mainly with the "via-first at trench level" approach, we found that most issues are similar in the other approaches.
 Figure 2. Severe topography in the full via-first approach can lead to severe resist thickness variations and subsequent differences in trench CDs. |
Photoresist chemical interaction
To make the dual damascene stack as simple as possible, the top hardmask can be omitted. This puts the photoresist in direct contact with low-k material. In some cases, we observed chemical interaction between the DUV-resist and the low-k film, leading to a problematic "foot" in the resist profile. For example, we observed this problem when a conventional single-layer resist was put directly on top of SiOC:H low-k material, produced by PECVD processing using trimethylsilane and N2O. Additional surface plasma treatments with O2 restored the resist profile control. Using this approach and also possible negative effects on the k-value (dielectric constant) of the low-k material by chemical reaction have to be investigated.
Reflection control and planarization
It is well known that reflection control is essential in lithography processing [1]. This is the reason that inorganic ARCs are added to dual damascene stacks. After creating topography in the first photolithography step, however, local reflectivity changes occur over the wafer (e.g., etched vias present at the metal trench print in the full via-first at trench level). Using a single-layer resist on this topography results in severe CD variations. This is the result not only of local reflection variations, but also of severe resist thickness variations because of changes in via topography density. Figure 2 shows that the CD of a short trench is affected by its position in the topography. A possible solution to this problem is the use of an organic BARC; this can help make reflectivity more uniform and also decreases via-topography.
 Figure 3. Across wafer uniformity measurements prove that CD-SEM measurements can be done with little noise in uniformity measurement. |
When looking at planarization using conventional BARCs, however, we learned that it is difficult to fill both isolated and dense vias in a similar way. Typically, in our experiments using via-topography, we found that isolated 250nm holes were filled quite easily, but that dense (1:1.2) 250nm holes only half fill (of course, this depends on via density and via size). So, it is difficult to predict how much planarization is required in a process, since partially filled vias already reduce reflectivity changes and resist thickness swing.
In most cases, one prefers a process where all possible via densities are completely filled with BARC in order to have no resist thickness variations. This requires planarizing BARCs with lower viscosity or multiple BARC coatings. In our work, we used a double BARC coating to planarize via topography in a via-first at trench level process. With all vias filled, the subsequent photolithography step with a single-layer resist yielded short trench CDs on target, independent of the position in the via-region. We realize that it might still be worthwhile to use a specially designed BARC for these applications, however, since the optical coefficients of conventional BARCs are optimized for thin layers.
Dry-etch resistance
Although our investigation showed that thick organic BARCs provide reflection control and planarization, this approach has some process issues. There are differences in BARC thickness in between vias, depending on via topography. Moreover, since in the subsequent metal trench etch the vias need to be cleared from the BARC, at least partially, this leads to long etch times for BARC opening. In general, organic BARCs have etch rates similar to conventional single-layer resists, so this approach requires rather thick resist — similar to, or thicker than, the thickness of the BARC-layer to be etched. This is an important disadvantage for CD control, especially with smaller dimensions and implementation with 193nm resists.
 Figure 4. Tests with 193nm TIS-2000 prove its feasibility for printing dense (1:1) and isolated 150nm features (sigma=0.6) using BIM. |
A thin imaging process
The issues described above can be overcome by separating the imaging properties of the resist system from the other requirements, such as reflection, planarization, and etch resistance. This can be done with the Arch Chemicals TIS-2000 bi-layer resist process [2], which uses a thin silicon-containing top imaging layer on top of a highly planarizing, fully absorbing underlayer (chemically similar to a novolak resist) with good etch selectivity properties. The processing sequence is similar to a process with organic BARC. This process can also be used for dual damascene patterning using both 248nm and 193nm lithography, meaning that dual damascene patterning can be scaled rapidly to 100nm technology without major modifications. (Two different underlayers and two imaging layer materials, the latter with only slightly different absorbances, are available.)
The very thin imaging layer on a planarized layer has the potential of very high resolution and, since it is silicon containing, it has a very high etch resistance during the underlayer etch. In addition, the TIS-2000 process uses conventional "track" processing and can be installed next to conventional resist lines without incompatibility issues.
 Figure 5. 160nm dense and isolated via patterning using 193nm TIS-2000 and a binary mask (ASML PAS 5500/900, 0.63NA, 0.4s). |
TIS-2000 planarization and fill behavior
We investigated planarization behavior, which is very important for the second photolithography step in dual damascene patterning both on via topography and metal trench topography. This was our way of checking the feasibility of implementing TIS-2000 in both damascene approaches.
Planarization on trench topography, which is present in the full metal-first at trench level process, is very difficult. The main issue here is that all sizes — provided they are larger than the design rule — are possible in combination with all pitches. This means that in principle a minimum-size isolated trench can be present as well as a minimum spacing between very large trenches. For the first, the full nominal underlayer thickness is present on the stack, while the underlayer thickness on top of an isolated line will be equal to the nominal underlayer thickness minus the topography step.
Therefore, planarization of trench topography requires an underlayer thickness higher than the topography step and results in a maximum long-range topography equal to the topography step itself. This consumes a large part of the depth of focus (DOF) of the metal trench photolithography step. Potential solutions include:
- the "partial metal-first at trench level" approach where the topography is much less severe, or
- the more difficult introduction of dummy structures in the design, giving an upper or lower limit to the trench "local pattern density" (LPD) (i.e., the ratio of area with designed trenches per area unit).
Planarization on via topography is in most cases less severe, since the via topography is less variable: On one hand, vias of only one size are present in typical designs, and, moreover, the maximum density is in most cases limited to about 1:1. This means that a typical maximum via LPD is about 25%, since in 1:1 dense via regions only one quarter of the area is filled with vias. On the other hand, the via depth can be significantly larger than in trench topography, especially in the "full via-first" approach, which tends to increase long-range topography difference for the imaging layer between dense and isolated via regions.
A rough estimate for the maximum long-range topography in the via-first approach is derived from the product of the maximum via LPD and the via depth since planarization length is much larger than the lateral via dimension. This estimate fits well with our experimental observation where 1.2µm-deep vias were planarized with the underlayer. We observed that the maximum long-range topography was about 275nm, which is close to the result obtained from the estimate discussed above. While this is less than a typical "full metal-first" approach, it still consumes a significant amount of the DOF budget. Again using the estimate, we can predict that "partial via-first" will result in approximately half of the maximum long-range topography, compared to "full via-first," since vias are about half as deep. This is an important advantage of the "partial via-first" approach toward the lithography process window.
Etch resistance of TIS-2000
At IMEC, we do underlayer etch using a SO2-O2-He process in a LAM TCP 9400 etcher. Using this chemistry, the etch selectivity between the patterned imaging layer and the underlayer is very high: we have observed that with an underlayer etch of ~1500nm the imaging layer is not significantly decreased in thickness. We observed only a slight tapering of the imaging layer at both sides of the etched trench.
Metrology issues
A potentially major issue is the shrinkage of the imaging layer from e-beam exposure during measurement with CD-SEMs after wet development. This phenomenon is similar to CD-SEM shrinkage effects observed in single-layer 193nm resists [3]. A solution to measure these resists uses "dynamic focusing" (i.e., focusing on another, close-by feature rather than the measurement structure).
Using this technique, we were able to achieve reliable measurements for the 248nm TIS system after wet development; for example, evaluation of 250nm isolated trenches with a 22nm 3sigma, with a tendency for slightly lower CDs in the center of the wafer (Fig. 3). While the underlying cause of the nonuniformity needs to be investigated further, the fact that a clear trend is visible in measurements with little noise proves that precise metrology can be done.
We did find that there was no linewidth shrinking after underlayer etch. Moreover, after underlayer etch the difference in linewidth between repeatedly (20 times) SEM-inspected trenches and the un-inspected trench was very small. Specifically, after underlayer etch the difference between inspected and uninspected 250nm isolated trenches was only ~10nm/side, much less than the 20-40nm expansion observed after 20 measurements.
Patterning performance
The lithographic performance of TIS-2000 has been demonstrated for different applications in various technologies [4]. A few examples are given in this section.
We evaluated TIS-2000 first for metal trench application, exploring limits using both 248nm and 193nm lithography [5]. We measured the process window for 150nm trenches exposed using a binary mask on the ASML PAS5500/900 stepper (NA=0.63,s=0.6) interfaced to a TEL ACT 8 track system.
Figure 4 shows that by using TIS-2000, a DOF and exposure latitude can be achieved for both dense and isolated trenches that is comparable to state-of-the-art single-layer 193nm resists.
TIS-2000 can also be used for printing 160nm and 140nm vias using respectively binary masks and alternate phase shift masks. In the latter case, the process window was not limited by sidelobes [4].
TIS-2000 also shows excellent patterning capability (Fig. 5). The silicon-containing imaging layer is a very good barrier for underlayer etch, resulting in ideal vertical profiles for the oxide etch. This is a clear advantage compared to conventional single-layer resists; due to slope and top rounding in the resist profile, single-layer resists easily induce faceting at the top part of the etched via.
Conclusion
At IMEC, we have implemented TIS-2000 successfully in different dual damascene integration approaches, mainly using an oxide dual damascene stack.
The feasibility of TIS-2000 in the "full metal-first at trench level" process is demonstrated in Fig. 6. Here, TIS-2000 was capable of patterning 250nm vias on top of severe trench topography. Clearly, for these dimensions the TIS-2000 has sufficient DOF to overcome the long-range topography.
For the metal trench level in the "partial via-first at trench level," a 550nm-thick underlayer was sufficient for planarization. Cross-sections revealed that this thickness was also sufficient for underlayer and oxide etch, since approximately 200nm of the TIS-2000 layer is still present on the stack after full etch. In this way, we demonstrated the capability of TIS-2000 to print 250nm trenches with various duty cycles on top of 250nm vias (Fig. 7).
Finally, electrical measurements on a one million via chain for 180nm technology (Fig. 8), where via and trench sizes are 0.25µm and achieved with TIS-2000, show that 90% yield can be achieved using the "partial via-first at trench level" approach.
Acknowledgments
We thank Patrick Jaenen for help in processing and Frieda Van Roey for underlayer etch. We acknowledge the fruitful collaboration and helpful discussions with the ARCH/FFO team at IMEC, including Grozdan Grozev, Mario Reybrouck, and Veerle Van Driessche, and the dry etch department, including Carine Alaerts, Tania Dupont, Muriel Lepage, Herbert Struyf, and Serge Vanhaelemeersch, as well as the P-line.
References
- M. Opdebeeck, et al., "Bottom-ARC optimization methodology for 0.25µm lithography and beyond," Optical Microlithography XI, Proceedings of SPIE, Vol. 3334, pp. 322-336, 1998.
- J. Biafore, et al., "Adjustment of bilayer optical properties and the effect on imaging and etching performance," Optical Microlithography XIII, Proceedings of SPIE, Vol. 4000, pp. 942-951, 2000.
- M. Neisser, et al., "Mechanism studies of Scanning Electron Microscope measurement effects on 193nm photoresists and the development of improved linewidth measurement methods," Proceedings of Interface 2000, pp. 43-52.
- I. Pollentier et al., "Dual Damascene back-end patterning using 248nm and 193nm lithography," Proceedings of Interface 2000, pp. 265-283.
- M. Maenhoudt et al., Proceedings of International Symposium on Microelectronic and MEMS technologies 2001, to be published.
Mireille Maenhoudt received her PhD in physics from the University of Leuven. She is responsible for dual damascene lithography and back-end process development at IMEC, Kapeldreef 75, 3001 Leuven, Belgium; ph +32 16-281-880, fax +32 16-281-637, e-mail [email protected].
Ivan Pollentier received his PhD in physics engineering from the University of Ghent in Belgium. He manages the process development group within the lithography department at IMEC.
Vincent Wiaux received his MS and PhD degrees in physics from the University of Leuven. His work at IMEC deals with issues in DUV dual damascene lithography and the application of OPC for back-end layers.
Diziana Vangoidsenhoven joined IMEC in 1995 and has been working as a research assistant in the lithography group, focusing mainly on process development.
Kurt Ronse received his MS and PhD degress in electrical engineering from the University of Leuven. Ronse is lithography department director at IMEC, responsible for a worldwide 193nm lithography development program.