Top surface imaging improves copper process resolution*
03/01/2001
Bill Gadson, Tactical Fabs Inc., Fremont, California
Steve Lassig, Nancy Tran, Tom Ni, Lam Research Corp., Fremont, California
*Based on work originally presented at the Arch Microlithography Symposium—Interface 2000.
overview
In a comparison to standard DUV lithography with bottom antireflection coatings, top surface imaging provides improved resolution in a via first, copper dual-damascene process. This technique effectively extends the range and use of binary masks. Delineation of the top surface pattern was accomplished using an SO2-O2 plasma etch. In addition, this process was extended to recess the via plug controllably to the level of the trench etch stop. This allows the etch process to transfer the trench pattern while retaining excellent fidelity of the dual-damascene structure. While the process latitude for critical dimension control was markedly improved, the difference between isolated and nested features was larger with the top surface imaging than with standard DUV. This difference may be reduced by optimization of the top surface layer develop process.
With copper dual-damascene processing, the most common integration approach is the via first scheme. In this process, via holes are etched through a dielectric stack stopping on a nitride barrier over copper. The resist is stripped, the trench is patterned and etched, and the barrier layer above the copper in the vias is opened to allow contact (Fig. 1).
After these steps, we must deposit, usually by sputtering, a thin conducting barrier material, such as tantalum or tantalum nitride, followed by a thin copper seed layer. A thicker, gap-filling copper layer is deposited using electroplating. In the overall process, these conducting layers will eventually be planarized by chemical mechanical polishing to form the metal interconnects.
 Figure 1. Patterning steps for a typical via first, dual-damascene integration scheme. |
It is important that the etch process does not expose the copper during the via etch or trench etch steps. Sputtering of copper onto the sidewalls would be a source for contamination and increased electrical leakage in finished devices. Exposed copper is also subject to oxidation from the atmosphere as well as various plasma-processing gases and this could result in unacceptably high via resistance. The barrier material must be removed with a gentler etch process; this is typically performed after resist strip. The trench etch, resist strip, and barrier-opening steps can be performed in one pass through an etch system.
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The trench patterning in the via first scheme is one of the most critical steps, both for lithography and etch. Using a standard DUV lithography process, a bottom antireflection coating (BARC) serves two purposes. It improves pattern resolution by reducing substrate reflections. In addition, the resulting partial fill of the via helps protect against potential exposure of the copper to the plasma environment. This allows minimization of barrier layer thickness, which is typically a higher dielectric constant material such as silicon nitride.
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Controlling via plug depth is critical to a trench etch process. If the plug is not recessed below the trench stop layer, the resulting feature may have a veil (i.e., "fence") around the via opening at the bottom of the trench (Fig. 2). Via depth, size, and density affect via plug depth [1]. Consequently, this can vary considerably depending on design rules, film thicknesses, and circuit layout. We have observed that via plug depth varies considerably within each die for most circuit layouts.
The resolution of trench lithography can vary considerably at the edge of large arrays of vias. As photoresist is spun onto wafers, it flows into vias. Regions with high densities of via holes act to reduce the resultant resist thickness (Fig. 3).
Bilayer surface imaging
We have found that for successful lithography and etch during the trench etch over a via step, a bilayer, surface-imaging technique addresses the problems of resolution, critical dimension (CD) control over arrays of vias, and the via plug depth control. All our work comparing single-DUV and bilayer resist processes (Table 1) was with 200mm silicon wafers with a sputtered 1500Å copper film and a chemical-vapor-deposited, dual-damascene dielectric stack; the copper simulated the underlying metal interconnect layer. The dielectric stack included alternating layers of silicon nitride and silicon dioxide (Table 2).
 Figure 2. Veils may result when a via plug is significantly above the trench stop during etch. |
After the imaging layer of the TIS 2000 process (Table 1, row 6) is exposed, baked, and developed, a dry-develop step is used to transfer the pattern to the underlayer using a SO2-O2 plasma at 5mtorr. Etching the underlayer to the dielectric surface below defines the trench pattern. At this point the vias are still filled and the trench etch would not be satisfactory, as explained earlier. Thus, we extended the dry-develop step to recess the via plug. Because the trench open area is large compared to the via area, an optical endpoint signal can be used to determine when the recess etching begins, providing good control.
 Figure 3. When using a standard DUV resist process, resolution of trenches can vary due to changing resist thickness, especially at the edge of dense arrays of vias. |
Figure 4 shows the fully recessed dry-developed structure before trench etch. The imaging layer has been thinned down, but is still intact indicating plenty of process latitude for the dry-develop and recess steps. Note that the plug is not flat across the via diameter, but tapers at the via sidewalls. This occurs due to sidewall reflections increasing ion bombardment in that area. We adjusted the recess etch time to keep the plug material at the sidewall below the intermediate etch stop layer. The profile of the trench lithography is still vertical, and cursory examination indicated that CDs had not changed. (This should be quantified for manufacturing purposes.)
We performed the trench etch using an Ar-C4F8-CO-O2 plasma at a pressure above 100mtorr. The result, shown in Fig. 5, has a nearly ideal transfer of the trench pattern with no veil or faceting of the top of the via inside the trench. Because the barrier (silicon nitride above the copper layer) is covered by the via plug during the trench etch, the required selectivity is not high. This allows the process to be adjusted for a wider process window and higher etch rates.
The reticle used for exposure was a binary mask with trench dimensions as low as 0.225µm, features difficult to resolve with the standard DUV process. Consequently, we compared the standard DUV process to the TIS 2000 process using slightly larger 0.250µm features; we performed exposure-focus matrices and measured CDs.
Data for the standard DUV (Fig. 6a) show the resolution of the isolated features to be close to the mask dimension for dense features when the exposure was 9.6mJ/cm2. The isolated features have a wider range with focus and are about 30nm to 35nm smaller. Note that the exposure window is quite narrow in that a 10% change in exposure results in ~12% (30nm) change in the CD. Operating below 9mJ/cm2 to access smaller geometries for this process would not be recommended.
Exposure-focus data for the TIS 2000 process (see Fig. 6b on p. 82) show a tighter distribution for focus, which is expected since the imaging layer is 2.5x thinner than for the DUV case. The realized CD appears to be smaller than the mask CD by about 30nm for the dense features. The variation of CDs for both the dense and isolated features is much smaller with exposure and focus settings. A 10% variation in exposure appears to result in <5% (~10nm) CD variation for both isolated and dense features. The variation between the dense and isolated features was unexpectedly higher than for the standard DUV case with more than 80nm difference.
Comparison of trench lithography at the edge of large via arrays shows another advantage of the top surface-imaging technique [2]. Figure 7 shows the trench pattern over via holes near the edge of the via array. The trench features, small connecting straps between adjacent via holes, change rapidly at the edge of the array as the thickness of the resist changes in that area for the case for a standard DUV process. The underlayer of the TIS 2000 completely fills the vias. Thus, the resist thickness is constant and there is little or no variation.
Conclusion
We compared standard DUV and bilayer surface-imaging processes for dual-damascene trench patterning in the via first scheme. With the DUV process, via holes partially fill with BARC and the depth of the via plug can vary significantly within a die. The via plug has been shown to cause via veils or fences in those areas where the plug persists above the trench stop layer. By filling the via completely as with the thicker underlayer of the bilayer, the via plug can be controllably recessed using an extension of the dry-develop step. The control of this step is expected to be quite good in a manufacturing environment due to the reliable endpoint for the dry-develop step. Indeed, we produced high-fidelity, dual-damascene features using this methodology.
 Figure 6. Exposure plots for different focus settings for the a) standard DUV resist and the b) TIS 2000 processes, both using a 0.25?m trench (binary reticle). |
The process latitude in terms of variation with exposure and focus for the top surface-imaging technique appears to be much wider than for standard DUV. In addition, minimum resolution using a binary reticle can be extended by more than 30nm for dense and more than 50nm for isolated features.
The underlayer of the bilayer process and the BARC layer serve similar functions with respect to suppressing reflections. Since underlayer is more than seven times as thick as the BARC, it can completely fill vias. This results in two advantages. First, the via plugs are all the same thickness and can be recessed uniformly. Second, the imaging layer that is spun on top is less prone to thickness variations and subsequent variation in CDs with topography.
We believe that we can extend the use of our binary masks to produce 0.20µm features or less. This is an advantage, since binary masks are considerably less expensive than phase-shift masks. Additional work needs to be done to compensate for the difference seen between the isolated and dense features.
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Figure 7. Trenches over vias near the edge of a dense via array: a) trenches that vary considerably for standard DUV lithography, and b) the same area with TIS 2000 resist.
While this work was performed using dual-damascene dielectric stacks of silicon dioxide and silicon nitride, we feel that this technique may be applicable to some of the low-k dielectric materials as well, including org-anosilicates (OSGs). One known problem with these films is that they may poison DUV resist when the resist comes in contact with the OSG material. This is the case for trench patterning over vias. The use of a single BARC coating does not suppress this problem. It is expected that the underlayer of the bilayer process we worked with would be of sufficient thickness to eliminate the DUV poisoning.
Acknowledgments
The authors would like to thank Eric Wagganer, Doug Keil, and Johan Vertommen (currently assigned to IMEC) of Lam Research for discussions and for help with some of the SEMs.
References
- C. Verove et al., "Dual-damascene Architectures Evaluation for 0.18µm Technology and Below," Proceedings of the International Interconnect Technology Conference, p. 269, June 2000.
- M. Neisser et al., "Applying a Thin Imaging Resist System to Substrates with Topography," Solid State Technology, pp. 127-132, August 2000.
Bill Gadson received his BS in general studies from the University of Texas at Dallas and his MBA in technology management from the University of Phoenix. He is the senior lithography technologist for Tactical Fabs Inc., 51 Whitney Place, Fremont, CA 94539; ph 510/770-8700, fax 510/770-8879, e-mail [email protected].
Steve Lassig received his BS and MS in materials science from Rensselaer Polytechnic Institute. He is the manager for process integration at Lam Research Corp.
Nancy Tran received her BS in chemical engineering from the University of Wisconsin, Madison. Tran is a staff engineer at Lam Research Corp.
Tom Ni received his BS and MS in chemistry from the University of Science and Technology of China and a Doctor of Chemistry degree from the University of Texas at Dallas. Ni is a principal technologist currently managing advanced applications in the New Products Division at Lam Research Corp.