Practical issues in the probing of copper pads
03/01/2001
Part Two of a Series
Timothy Turner, Keithley Instruments Inc., Cleveland, Ohio
overview
Copper metallization introduces new challenges for wafer probing. Material effects such as grain size and processing issues such as CMP dishing must be accounted for during probing. Testing techniques to do this have been developed. Accurate and fast Cu probing solutions are now available.
With the switch from aluminum (Al) to copper (Cu) interconnects to improve semiconductor performance, one thing remains the same. Electrical testing of semiconductor devices at the wafer level still requires the use of sharp probes placed on probe pads. However, Cu metallization has introduced significant problems associated with probing.
Probe contact issues
Al is a very soft material. When a probe is pushed across an Al pad, it penetrates the surface somewhat and produces scuff marks where Al metal has been pushed aside. Cu is significantly harder than Al, so Cu pads typically do not show probe marks. This characteristic creates two practical issues associated with the probing of Cu pads.
 Figure 1. Probe contact can be verified visually with Al pads, but not with Cu, which requires a resistance or capacitance measurement to detect probe contact. |
The first issue arises from the fact that probe marks are generally used to verify probe contact and set the Z (height) probing dimension (Fig. 1a). With Al pads, proper Z adjustment for a wafer prober can be verified by inspecting the pads for probe marks after a wafer site has been contacted (Fig. 1b). For example, if one probe needle is slightly higher than the others in the probe set, it may not contact the probe pad. This can be seen easily with Al pads, because there are clearly visible probe marks on all pads except the one where the probe needle failed to make contact. This can usually be corrected by increasing the overdrive slightly. With Cu pads, however, there are no visible probe marks on any pads (Fig. 1c).
The inability to verify probe contact visually on Cu pads means that an electrical verification procedure is required. There are two electrical contact measurement techniques that can be used. The most straightforward technique is to use a probe pad set where all of the pads are connected together (Fig. 2). This allows contact verification with a measurement of contact resistance (Fig. 1d) by simply forcing current between pairs of probes.
This simple technique provides excellent resistance resolution and a short test time. However, it does require that a probe pad set be dedicated to this measurement. This is most practical for technology development where significant areas of the entire wafer are covered by test structures, but this solution may not be practical for production monitoring where probe pads must be placed in a scribe lane, or when contact to semiconductor devices must be verified.
The second technique used to verify electrical contact is a capacitance measurement. The capacitance of each probe needle is measured relative to the chuck before wafer contact is attempted. After the probes are placed on the wafer, the capacitance is measured again. There will be a significant increase in capacitance due to pad contact and the circuitry attached to the pad (Fig. 1e). If a probe does not contact a pad, the measurement will show only a small capacitance change from the non-contact measurement.
 Figure 2. Contact resistance measurements are usually done with all of the pads connected together. |
Besides contact verification, the capacitance can actually be measured as the Z height is adjusted so that the contact position is detected electrically. This measurement of electrical contact does not require any special test structures, but it does require a very fast capacitance meter to make such measurements practical. Furthermore, to get the speed and resolution required to make these measurements in a production setting, the parametric test system requires careful design. For example, in the Keithley Model S633 parametric test system, a fast VXI interfaced C-meter is used, with the front end of the C-meter duplicated on each test head pin. This combination provides very fast, high-resolution C measurements for probe contact verification while consuming an insignificant percentage of a typical wafer site's test time. The capacitance technique is practical for both production monitoring and final device testing. It does not, however, provide the contact resistance measurement capability that the "shorted probe pads" technique does.
Contact resistance increase
With the usual tungsten-based wafer probes, Al metal has very low contact resistance, but there is more to the story than that. Al rapidly grows a thin native oxide surface coating within seconds of air exposure. This thin Al2O3 layer adheres well to the underlying Al metal, and the growth of this layer passivates the metal to prevent further oxide growth. Mechanically probing an Al pad causes penetration of this oxide layer, which must occur in order to contact unoxidized Al and create a low-resistance connection. In fact, Al is soft enough for the probe's force to distort the metal and cause it to conform to the rounded probe surface. This increases the contact area and further reduces contact resistance. Also, since Al2O3 adheres well to Al, there is little probe contamination associated with the oxide layer.
Cu is a near noble metal that oxidizes slowly. The oxide does not adhere well to the underlying Cu metal and does not passivate its surface. Further, the probe does not cause significant deformation of a Cu pad, leaving minimal scuff marks on the contact area. These characteristics of Cu increase probe contamination problems compared to Al pads. Figure 3 shows the contact resistance change that can be expected for Cu and Al pads as a function of the number of probe contacts/probe needle. The faster increase with Cu pads is a result of probe contamination.
Contact resistance can be returned to low values by cleaning the probes. Probe cleaning is typically done by contacting the probes with a "cleaning pad." Several prober manufacturers are now including an optional "cleaning block" or "pad" to remove probe contamination. Sliding the probe needle tip across the cleaning block reduces surface contamination and contact resistance. This is accomplished by simply controlling the Z height of the probes when they are positioned over the cleaning block. Since the cleaning block is abrasive to the probe tips, though, the number of cleaning cycles/probe needle is limited.
 Figure 3. Cu pads require more frequent probe cleaning to maintain accuracy. |
The increased susceptibility of probe needles to contamination from Cu pads requires careful monitoring of the number of pad touchdowns and cleaning cycles for each probe card. This information is critical for assuring reliable test results when probing Cu pads. This data can be maintained in a central computer file, or in "smart" probe cards. Smart probe cards include flash memory chips that store the number of touchdowns since the last cleaning cycle and the total number of cleaning cycles. This data is read by the parametric tester when the probe card is installed and is updated after each use. The information is then used to initiate the next cleaning cycle or to initiate a rebuild of the probe card when appropriate.
While Cu pads cause probe tip contamination, they create less particulate contamination than Al pads.
Since probes disrupt the oxide surface of Al pads and the Al metal itself, this produces particles of oxide and Al. Although the oxide is relatively inert, the Al particles contaminate and interact with wafer devices and processes. This can cause yield loss if the probing is performed prior to completion of wafer fabrication.
Probing Cu pads does not cause significant particle generation. Thus, probe testing of wafers can be accomplished earlier in the production process. This becomes more and more significant as the number of metal layers continues to increase. With Cu pads, process control parametric testing can be started at the first metal layer without a significant yield penalty. Depending on the number of metal layers, this shortens the time required to get important process control feedback by 50% or more. It follows that this allows faster yield improvement and reduces the inventory at risk if a production problem is detected.
 Figure 4. Cu sheet resistivity varies not only with linewidth, but also with other process variations. |
Monitoring complex Cu processes
Dual damascene Cu processes are much more complicated than most Al processes. Al processes typically involve sputter deposition (which may include a barrier deposition and ARC layer deposition process in situ), plus a plasma metal etch process. The Cu dual damascene process includes steps to define and etch trenches into an oxide, a barrier metal deposition process, a Cu seed layer deposition process, a Cu electroplating process, and a CMP process. Each of these process steps needs to be controlled, because each introduces potential process variation and interaction effects. A dual damascene Cu process therefore requires a dramatic increase in the number of process control parameters that are monitored.
 Figure 5. CMP dishing is caused by a higher removal rate on Cu compared to the dielectric. This is a linewidth-dependent effect that changes the resistance of the Cu layer. |
Figure 4 compares the sheet resistivity of a Cu film on a semiconductor product. This graph shows the resistivity as a function of the linewidth. In contrast, the resistivity of an Al film is nearly independent of linewidth. The dependency of Cu resistivity on linewidth arises because of a barrier metal layer used in the dual damascene process. This barrier, applied to the sidewalls of the Cu line, is required to prevent interaction between the Cu and the sidewall oxide.
 Figure 6. A "box cross" test structure is useful for detecting Cu process variations. |
The barrier metal layer has a near negligible effect on the measured sheet resistivity of wide lines, but it can be a significant portion of the total cross-sectional area on narrow lines. Thus, the measured sheet resistivity will show an apparent increase with smaller linewidths, as shown in Fig. 4 (section C compared to section D). Section D of Fig. 4 shows an increase in the sheet resistivity with a larger linewidth. This is due to the CMP dishing effect. This effect is seen when the CMP removal rate for the Cu is higher than the removal rate of the dielectric surrounding the metal lines. Wide lines will show thinning in the center of the lines as shown in Fig. 5. In some processes (with some low-k dielectrics, for example), the removal rate of the dielectric can be higher than that of the Cu. In this case, CMP dishing will not be seen.
The increase in resistance seen in section B of Fig. 4 is caused by the smaller metal grain size in narrower metal lines. When the linewidth is less than about three times the metal grain size, this effect becomes noticeable. Section A reflects the change in sidewall barrier thickness once the linewidth becomes less than about four times the barrier layer thickness.
In earlier Al processes, a simple set of two metal resistors of different widths, or a van der Pauw cross and a single metal resistor, were sufficient to calculate both the metal resistivity and the linewidth. However, with the more complicated linewidth/sheet resistivity relationship associated with Cu, many more measurements are required. Sidewall barrier metal thinning, Cu grain size reduction, the sidewall barrier sheet resistivity effect, and CMP dishing are all independent phenomena that need to be controlled in a process.
Effective process control monitoring therefore requires a minimum of four independent measurements. Generally, a single resistance measurement can be made to estimate each of these effects using Cu metal lines with different widths. A "box cross" test structure can be used to measure the Cu sheet resistivity independent of the sidewall barrier layer (Fig. 6). This is especially useful for the measurement of CMP dishing and the Cu grain size effect.
The box cross test structure provides valuable information for Cu processes, but its use for low sheet resistivity Cu will push the limits of available instrumentation. The voltage drop, which must be measured across this small test structure, will be a function of the forced current magnitude. The current that can be forced through the structure is limited by joule heating in the narrow metal lines that connect the box cross structure.
Joule heating will change the resistivity of the Cu metal by about 0.36%/°C of heating. Figure 7 shows a graph of the required voltage resolution needed for a measurement of the sheet resistivity using a box cross structure. The resistivity is a function of the width of the line connected to the structure. Measurement of voltages this low requires an excellent differential voltmeter and the averaging of two measurements made with current flowing in opposite directions. This technique removes the "battery" effect that is created at the junction of dissimilar metals, i.e., the tungsten-based probe needle and Cu pads.
Defect density considerations
Defect density is another issue that affects Cu processes and how they are monitored with parametric testers. Defects in a Cu metal process include opens, shorts, and resistive shorts. Opens are generally caused by excessive CMP etching in local areas, due to situations like a particle on the backside of the wafer. Shorts come from particles or areas where the CMP process has not removed all of the original metal over the oxide between the oxide trenches. There can also be shorts formed due to cracks in the dielectric between trenches, which are generated during the CMP process initially or by metal/dielectric stress induced by thermal treatments later in the process. Stress migration effects are reduced for Cu compared to Al, but they are not eliminated. Stress migration can cause opens in the interconnect system.
Shorts and opens have always been problems associated with Al metallization, but the industry has developed effective detection and control methods for these problems. The issue of resistive shorts is a new problem associated with Cu. Resistive shorts come from cracks or pinholes in the barrier metal surrounding the Cu on three sides. When Cu is in contact with silicon dioxide, there is a rapid reaction between the two. This increases the resistivity of the Cu locally and reduces the dielectric isolation between adjacent metal lines.
The detection of resistive shorts generally requires low current measurements at high voltages. This resistive short phenomenon is a reliability issue complicated by the fact that the Cu/dielectric reaction can occur even at typical usage temperatures. Thus, areas with defects in the barrier metal layer will exhibit increasing leakage and increasing local line resistivity during the life of the device.
Defect detection requires large area test structures, with the required area being determined by the lowest defect density that must be measured. Such large structures are usually found only in process development wafers. Traditionally, a long serpentine defect density structure has been used to discover defects associated with resistivity increases. The resistivity increase at a local defect is, though, hard to detect in a long serpentine structure. This is because a small defect will have a very small impact on the resistivity of a long line.
The leakage associated with such a defect is much easier to detect in a large test structure. Generally, this leakage can be detected by forcing a voltage between two interdigitated comb structures and measuring low currents. The voltage that must be forced is typically a voltage that generates an electric field of 10MV/cm in the remaining oxide, assuming that a defect is defined as one that reduces the sidewall oxide thickness by 25%. Detection of leakage in the neighborhood of tens of picoamps is usually sufficient to detect potential reliability defects of this sort.
Still, this is not a trivial measurement. Figure 8 shows voltage forced on the test structure as a function of the minimum space between two metal lines. At some point, the required current measurement pushes instrumentation capabilities, as parasitic leakage associated with some test equipment may approach 10pA/V. An instrument with this level of leakage will not be able to measure less than a few nanoamps at voltages above 100V. Instruments with a parasitic leakage as low as 1fA/V are now available.
Conclusion
The introduction of Cu metal into modern semiconductor processes complicates wafer probe testing techniques. However, the issues associated with Cu pads and interconnects are now well known, and solutions have been developed. Still, it is important to understand the differences between Cu and Al probe testing to assure that test equipment and techniques provide both speedy and accurate results when dealing with Cu.
Timothy Turner is director of structures engineering in Keithley's Semiconductor Division, where he is responsible for design and development of wafer test structures and device reliability algorithms. He previously operated Turner Engineering Technology, specializing in accelerated test methods for semiconductor fabs. His 25 years of experience in semiconductor reliability includes work at the Reliability Analysis Center in Rome, NY and Mostek Corp. He has been issued six US patents in the field of semiconductor processing. Keithley Instruments, 30500 Bainbridge Rd., Cleveland, OH 44139-2216; ph 440/498-2874, fax 440/498-2911, e-mail [email protected].