Trends in void-free pre-metal CVD dielectrics
03/01/2001
V.Y. Vassiliev, J.L. Sudijono, A. Cuthbertson, Chartered Semiconductor Manufacturing Ltd., Singapore
overview
Prevention of voids in CVD dielectrics is an increasingly difficult challenge as gap spacing decreases. A systematic review of the gap-fill capabilities of several CVD processes identifies trends and likely future directions.
The drive toward the 100nm technology node and below includes a decrease in device gap spacings in conjunction with an increase in aspect ratios at the transistor level [1]. Small gaps with a spacing below 0.1µm and an aspect ratio (AR) higher than 3 have already become a feature of 0.18µm device technology. A decrease in the gap spacing goes along with a change in the gap shape, and a re-entrant gap profile is common in ULSI devices. This factor, plus traits of CVD film deposition, contributes to voiding in pre-metal dielectric (PMD) gap-fill processes.
 Figure 1. Schematic diagrams of void formation: a) after CVD film deposition, b) after insufficient BPSG film flow, and c) after HDP-CVD film deposition. |
Two major options are considered for future PMD applications. The first is the continued use of borophosphosilicate glass (BPSG) films [2]. These ternary glass films have an intrinsic flow property due to the temperature dependence of glass viscosity (u). A post-deposition thermal anneal provides planarization of the film surface and a gap-fill improvement due to the elimination of as-deposited key-holes in certain device gaps. At low thermal budget conditions, however — rapid thermal annealing (RTA) at temperatures of 800-900°C, for instance — key-holes in small gaps transform into voids with a round shape when film flow is inadequate (Figs. 1a and 1b). Known solutions to this use higher pressure and wet ambients, but these are not suitable for many types of logic device technologies. Higher BPSG dopant content or more complicated germanium-doped BPSG films also allow for an increased efficiency of flow [2-4]. Nonetheless, moisture absorption and defect formation in highly doped glass films (including germanium-doped films) are the big challenges for these solutions [5, 6]. Hence, traditional flowable BPSG films with a 10% (by weight) limit on dopant concentration are the best options for flowable PMD materials.
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The second option for the gap-fill PMD process is a high-temperature, high-density plasma (HDP) CVD technique for phosphorus-doped glass (PSG), and undoped silicon glass (USG) films. These films have excellent gap-fill capability because of in situ sputtering of material from the top surfaces of structures [7]. In contrast to the flowable BPSG films, the HDP option enables a void-free PMD gap-fill deposition without any further thermal treatment, but some voiding issues were also found in HDP-CVD PSG/USG films [8], as shown in Fig. 1c.
Thus, both of these options have limits. In this article we have generalized the data of the PMD gap-fill capability of flowable and HDP-CVD films. A comprehensive view of PMD gap-fill issues has been created, and directions for advanced PMD for future ULSI device technologies have been proposed.
Previous experiments
Recent experimental data for BPSG films deposited at sub-atmospheric pressure and for HDP-CVD films are presented in Table 1. The gap profiles studied are shown in Fig. 2. SEM cross-section images of test structures allow plots such as that in Fig. 3a, showing the critical gap spacing and AR conditions (G>Gcritical and AR<ARcritical) for void-free PMD gap-fill.
An analysis of void height in the voiding area of Fig. 3a is presented in Fig. 3b, with the void height normalized to the gate thickness. It shows generally that void height increases with a decrease in gap spacing. Glass flow capability allows a significant decrease in the voiding, and there were no voids found in structures after a prolonged furnace anneal at 850°C of as-deposited sub-atmospheric BPSG (SABPSG) films. However, low thermal budget annealing conditions (such as RTA) do not allow full elimination of key-holes, as can be seen in Fig. 3b.
 Figure 2. Typical gap profiles before PMD gap-fill: a) re-entrant, b) tapered, c) vertical, and d) partly vertical. |
Gap-fill performance of flowable BPSG films
Voids have become a bigger problem with the reduction of thermal budgets. This has been seen mostly for the vertical and especially re-entrant gap profiles. To understand features of film flow, we have introduced a quantitative description of the viscous behavior of BPSG films during annealing. We proposed that the change of the angle on a device step from A0 to At will follow film viscosity and, therefore, can be expressed as At = A0xeE/RTxCt, where Ct is an additional term to account for the time dependence. SEM cross-sectional analysis of a number of test structures with as-deposited and annealed BPSG films allowed us to obtain empirical equations for the angle At, which include anneal temperature Ta (K), boron [B] and phosphorus [P] concentration in wt.%, step coverage angle A0, and anneal time t. The following empirical equation was derived for BPSG films with furnace anneal:
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A similar equation has been derived for RTA conditions and is found to fit experimental data with good accuracy. Furthermore, these equations allow us to perform a pareto analysis of the impact of process parameters responsible for BPSG film flow [9]. For the case of furnace anneal, the following parameters are important in descending order: anneal temperature, step coverage, [B] and [P], and anneal time. Identifying this ranking list is useful for understanding the competing effects on film planarization, especially the anneal temperature and step coverage.
As-deposited CVD film step coverage and gap-fill
During the filling of structure gaps with CVD films, an aspect ratio value increases dramatically before the gap is closed (as shown in Fig. 4) for certain perfectly vertical device gap structures and strongly conformal CVD film deposition. However, CVD films normally reveal nonconformal step coverage because of the nature of gas-phase reactions during film deposition, and because of the diffusion into narrow gaps that eventually leads to the void formation. Since step coverage has a very high impact on film flow planarization, the as-deposited gap-fill structure also influences post-reflow gap-fill capability.
CVD process features are very complicated and different from one chemical system to another. To characterize them and to compare silicon-based CVD processes, we have proposed a general CVD parameter "effective constant of deposition rate" (Keff) [2, 10]. Comparing data for many studied chemical systems and CVD reactions, we found that they can be classified into several specific groups with different CVD features that have been explained with differences in reaction mechanism and limiting steps. These selected groups for oxidation reactions (labeled with letters) are shown in Table 2, and more data have already been published [10]. Film step coverage was found to be worse with an increase of Keff (Table 2). Thus, the best step coverage is found with a TEOS-ozone deposition process having a very low Keff. The worst step coverage — even zero coverage of the bottom of device elements — is a typical feature of highly accelerated and non-optimized oxidation processes, or plasma enhanced CVD. Using obtained values of Keff, the existing CVD processes can be generally ranked in order of worsening step coverage (and, therefore, gap-fill capability) as follows: LPCVD > APCVD > PECVD » non-optimized PECVD. A tapered gap profile gives rise to better step coverage of CVD films, while vertical and, especially, re-entrant profiles make it significantly worse.
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HDP-CVD films
Since HDP-CVD films are considered to be non-flowable, this process must provide the necessary PMD gap-fill in its as-deposited state. To date, the use of the HDP-CVD technique at a relatively high deposition temperature gives a much better PMD film gap-fill when compared to other known techniques [8]. At the same time, certain gap-fill limits have been found during an analysis of vertical structures at certain HDP-CVD conditions; particularly, etch to deposition ratios (E/D) of about 0.15. The general trend of HDP-CVD capability can be clearly seen from the comparison of processes in Table 2. Unbiased deposition, with very high Keff (about 15-20), is known to provide extremely bad step coverage [11, 12]. In addition, in situ sputtering of HDP deposited film does not seem to be effective for very small gaps. In fact, the behavior of voids has been found to be different from that in flowable BPSG films (see Fig. 3b). Further development of HDP-CVD techniques requires a decrease in E/D ratio down to 0.05, which will help to reduce re-deposition and will therefore improve gap-fill [13]. At the same time, gap profile is found to strongly affect the HDP-CVD gap-fill capability [8], implying that re-entrant gaps are expected to be very difficult to fill even with modified processes.
Generalized scheme of PMD gap-fill
In order to create a general view of PMD gap-fill approaches, we have summarized the specifics of CVD film flow capability and gap profiles using the generalized diagram shown in Fig. 5a [14]. The horizontal axis represents the film's ability to flow at enhanced post-deposition anneal temperature. The vertical axis represents a set of gap parameters, termed "structure complexity," such as spacing, aspect ratio, and shape. This parameter increases with a shrinkage of device design rules. Thus, gaps with a certain "structure complexity" value can be either successfully filled with PMD materials during film deposition and anneal, or not. An increase of glass flow will lead to improvement of PMD gap-fill, i.e., a higher complexity structure can be filled without voids in the dielectric. This allows us to derive a line between voiding and void-free areas (solid line in Fig. 5a), where any coordinates above the drawn line represent structures with voids in gaps, and any coordinates below the drawn curve represent void-free structures. Extremely high thermal anneal conditions correspond to full film surface planarization, with very small gaps being filled with a liquid glass. In contrast, if the flow becomes worse due to the changes of any flow parameter (either glass composition or thermal anneal conditions), the gap-fill capability is worse. At zero glass flow, the vertical axis represents gap-fill for as-deposited films.
This diagram reflects changes in film gap-fill capability for different gap profiles, as shown by dashed lines in Fig. 5a. This figure reflects that as-deposited film gap-fill is much better for tapered structures, as compared to the vertical or re-entrant structures. Also, significantly tighter structures can be filled with flowable films if structure tapering is used. In terms of the CVD process, an improvement in CVD film conformality should give us smaller key-holes. Obviously, better as-deposited film gap-fill will lead to the better post-flow gap-fill, as shown in Fig. 5b.
Quantification of PMD gap-fill
For numerical characterization of the proposed glass flow capability metric, we introduce the parameter (1-At/A0), which can be calculated using the equation shown above for known dopant concentration and post-deposition film anneal parameters. To characterize structure complexity, we have proposed — based on analysis of a large set of experimental gap-fill data obtained with LPCVD, APCVD, PECVD, and HDP-CVD films — that a ratio of AR to the gap size G can be used. This ratio represents the tangent of straight line drawn through the critical point, as shown in Fig. 3a. Taking into account a correlation of AR and gap height, this ratio can be expressed as a H/G2, where H is the structure height and G is the gap size. Additional structural descriptions, such as vertical, tapered, and re-entrant, also need to be taken into account. The decrease in device design rules means that gaps become significantly smaller, but the thickness of structures (i.e., gap height) becomes only slightly smaller. For instance, for a gap height of ~0.2µm of a vertical structure with gap values of Gv = 0.1µm and Gv = 0.05µm, the structure complexity (SC) can be calculated to be SC0.1 = 20 and SC0.05 = 80, respectively. An analysis of experimental gap-fill data has been presented previously [14].
Directions for PMD gap-fill
Figures 5a and 5b show two directions for PMD gap-fill improvement with CVD glass films. The first direction is elimination of key-hole voids using a post-deposition treatment, which can be more effective with enhanced glass flow capability (e.g., with high dopant concentration, high anneal temperature and long anneal time, or high anneal pressure and wet ambient), and with the use of tapered structures. In view of the well known BPSG film dopant restriction, as well as the trend toward low thermal budget conditions, the PMD gap-fill improvement using this approach is not adequate in itself.
 Figure 4. The change in aspect ratio value during conformal CVD film gap-filling of a gap with a vertical profile and height of 0.2µm. |
The second approach is to avoid or minimize the formation of key-holes in as-deposited film by improving film step coverage. On one hand, it can be done easily with the use of device structures with tapered gap shapes. On the other hand, a deposition process modification is necessary to affect film step coverage. Generally, it means complication of a CVD process in order to obtain new process features. Such modification can be illustrated by a two-step BPSG deposition process with the first step having a low deposition rate [15, 16]. Another option is a fluorinated SABPSG film [16], which also provides a lower as-deposited film step coverage angle A0 and, therefore, better as-deposited gap-fill. Both of these modifications give rise to better gap-fill [16].
Another possibility is a reduction of Keff by, for example, suppression of the gas-phase reaction. This is proposed for the non-optimized processes with extremely high deposition rates. Such approaches with special gas-phase additives have been discussed earlier for CVD oxidation processes [17], but generalized data in Table 2 show that this is applicable for plasma enhanced CVD or HDP-CVD processes [18]. Second, a modification of HDP growth profile by introducing isotropy in the sputtering component (i.e., with a certain lateral etch component), is also proposed [19]. These measures are not expected to lead to the total solution of PMD film gap-fill issue, however. Void behavior (Fig. 3b) shows that limits of HDP-CVD seem to be persistent regardless of any process optimization, especially with a trend of decreasing gap.
We conclude that, for the best improvement in PMD gap-fill, HDP-CVD BPSG films [20] have the most promising as-deposited gap-fill, with the remaining voids eliminated by subsequent film anneal at low thermal budget conditions (Fig. 5b). This gap-fill improvement in both as-deposited state as well as with additional margins from BPSG flow will lead to the complete solution for PMD gap-fill requirements for future ULSI devices.
Conclusion
Major limits of pre-metal dielectric gap-fill with CVD films for deep submicron device technology have been determined and quantitatively analyzed. A generalized quantitative diagram linking the gap-fill capability of flowable PMD CVD glass films and device structure complexity is presented. It is proposed that, for advanced device technology with extremely small and re-entrant gaps, PMD gap-fill improvement can be achieved using HDP-CVD BPSG films.
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Vladislav Vassiliev received his PhD in physical chemistry from the Novosibirsk Institute of Solid State Chemistry. He joined the Novosibirsk Semiconductor Devices Plant in 1976 and was the technical director and chief technologist of the industrial research module prior to joining Chartered Semiconductor Manufacturing Ltd. At Chartered, he is responsible for developing thin films for various CMOS logic applications.
John L. Sudijono received his PhD in physics from the University of Michigan at Ann Arbor. He was a research fellow at Imperial College in London, developing GaAs materials for optoelectronics applications. He has been involved in various activities in the BEOL module integration at Chartered since 1996. Chartered Semiconductor Mnfg. Ltd., 60 Woodlands Ind. Park D., Street, 738406, Singapore; ph 65/3604172, fax 65/3622945, e-mail [email protected].
Alan Cuthbertson received his PhD in 1984 from the University of Southampton, England, in the area of high-speed bipolar devices and BiCMOS. He has worked in the areas of CMOS logic and DRAM for Philips Research and Siemens, respectively. Prior to joining Chartered in 1996, he spent five years in the CMOS development group at IMEC in Belgium. He is currently director of technology development at Chartered, with responsibility for 0.13µm process development.