Thinking in 3-D: North etches copper bump connections for low-cost system-in-a-package*
03/01/2001
The Japanese venture North Corp. says its new technology to join copper circuit layers with copper bumps makes a direct copper-to-copper connection that's both reliable and cheap, potentially making it practical to stack several chips in one package.
Connecting a system of existing logic and memory chips together into one package instead of designing a new combined system on one chip would greatly reduce development time. But conventional wire bonding or solder bumps are not reliable enough for the vast number of minute connections required. Stacking the chips on buildup board, connected with copper-plated via holes, is reliable, but opening and plating all those holes gets expensive, and only gets more so with finer geometries.
 North uses low-cost processes for its neo-Manhattan bump interconnections. |
North's neo-Manhattan bump interconnection approach reportedly makes a highly reliable connection by etching out a layer of copper bumps to connect to the next layer of copper foil (see figure). Although it's commonly assumed that direct copper-to-copper connections can only be made in a vacuum, a North spokesman says it appears that such a connection is formed locally as fresh copper is pushed out on the connective surface when the two layers are pressed together. Etching the copper bumps also costs less than drilling and plating many fine via holes. Toshiba Corp. has a similar process of joining stacked chips with metal bumps, but its B2IT product uses screen-printed silver bumps, a technique harder to handle at very fine pitches. North says it can etch bumps down to a pitch of 150µm, and plans to do so by next year. Most of the process, including copper etching, uses existing printed circuit board production equipment.
Although the little 30-person printed circuit board maker has been around since 1985, North has gotten lots of attention lately as one of Japan's new breed of technology ventures. It attracted some $8 million in Japanese venture capital last year, and is spending about half the money on a new manufacturing plant in Fukushima, where it will make these low-cost copper-bump interposers. — Masahide Kimura, Keiji Sowa, Nikkei Microdevices, December 2000 (For more details, see www.northcorp.co.jp.)
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Sekisui and Chemitronics show nonvacuum plasma CVD equipment*
Sekisui Chemical Co. Ltd. and Chemitronics Co. Ltd. drew big crowds at December's Semicon Japan with their evaluation model low-pressure plasma CVD equipment. The $8.4 million maker of plastics and prefab housing, and the 30-person, $8.5 million semiconductor equipment venture have together developed plasma CVD equipment that doesn't need a vacuum chamber. "High-speed film production of several microns/min at 150°C is possible by increasing the plasma density without having to use troublesome vacuum processes," says the process's inventor, Motokazu Yuasa, who is manager of the P2 project in the semiconductor unit of Sekisui's high-performance functional plastics business.
Plasma usually changes instantly from a stable glow discharge to an unstable arc discharge at atmospheric pressure, so semiconductor makers use a vacuum chamber to maintain the glow discharge. But they'd love to get rid of the vacuum process, especially since increasing numbers of circuit layers means higher costs for plasma deposition of more intervening layers of insulation.
Previous low-pressure plasma technology used helium, but required too much of the expensive gas to be practical for production. Sekisui's new method depends instead on controlling the applied voltage. Gas is pumped in between the electrodes and a pulse of voltage applied, creating a glow discharge. Before the glow can change to an arc discharge, the voltage is decreased. Then before the glow fades, the voltage is applied again.
Deposition and etching without vacuum chambers could eliminate the need for batch processing. A continuous conveyer-belt production process "is not a dream," says Yuasa. He says film quality depends on the gas flow and the pulse voltage application, but can match the usual SiO2 in electrical and etching characteristics. Efficiency of materials usage is 50%-60%, higher than conventional vacuum CVD methods. Nonvacuum plasma CVD technology could also mean several times higher throughput and 20-30% lower costs. — Masahide Kimura, Nikkei Microdevices, January 2001 (See more details in Japanese at www.sekisui.co.jp)
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Lack of consensus: Japanese research plans stumble
Japan hopes to jumpstart its international competitiveness with a new generation of national research projects, but seems to be having trouble reaching a consensus on just what to do. Inspired by the role of Sematech in the US industry's development, the Japanese government will fund a seven-year national research project on next-generation materials and processes starting in April. Nicknamed MIRAI, which means "future" in Japanese, the project will focus on developing low-k and high-k dielectrics, and other materials and processes for 0.07-0.05µm system chips.
But a companion industry-sponsored research consortium, the ASUKA project, isn't getting full industry support. That research consortium had planned to start developing both design and process technology for 0.1-0.07µm system chips in April, but now appears to be scaling back its goals.
"Though MIRAI is a must to strengthen the Japanese semiconductor industry," says a highly placed Japanese industry source, "many Japanese semiconductor industry people do not feel the necessity of the ASUKA project. Major companies have already started their own 0.1µm process development and can't wait until the government's cleanroom becomes operational. Collaboration is not necessary at this technology node." Nikkei Microdevices reports that the organization hasn't raised enough money to fund its fine-process research technology at a competitive level. There is also grumbling that ASUKA's leadership and members are exclusively Japanese, when a leading research institution would need to be more international.
No one objects to the government spending its money, so the MIRAI project will start up April 1 as planned, under the direction of Masataka Hirose of Hiroshima University. He will also take charge of the Next Generation Semiconductor R&D Center, a new national lab to be established in Tsukuba, Ibaraki prefecture. Though the initial budget will be only about 3.8 billion yen (US$35 million), that's expected to dramatically increase in the future.
The government is also investing some 16.5 billion yen (US$150 million) in a 4500m2 cleanroom for the projects, though it won't be ready for more than a year, around April 2002. University researchers, semiconductor company engineers, and government researchers will work together to develop next-generation process technology. One major goal is to restore the competitiveness of Japan's semiconductor equipment industry. Tadahiro Ohmi of Tohoku University will also use some of the cleanroom space for his government-funded project to develop efficient low-volume "minifab" production processes.
The industry-funded ASUKA project plans to rent space in the new government cleanroom in Tsukuba for a small pilot production line. This project takes its acronym ASUKA from Advanced System-on-a-Chip Acceleration, but the name also refers to a sixth-century Japanese era known for vast social change and the birth of a flourishing native culture. The industry's 300mm equipment evaluation program Selete will move from Yokohama to Tsukuba and take charge of running the ASUKA project as well. Original plans for ASUKA called for the project to focus particularly on developing the technology and supporting infrastructure for the design side of 0.1-0.07µm system-on-a-chip devices, as well as the masks and process materials.
And one prime agenda was for industry to work more closely with Japan's universities to improve the skills of the students coming out of the system. — Staff Reports
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*These stories were translated for SST from Nikkei Microdevices, our partner in Japan.