Next-generation litho progress, innovative technologies at MRS
02/01/2001
Next-generation litho progress, innovative technologies at MRS
Steady progress in next-generation lithography, from resists for 193nm and 157nm systems to extreme ultraviolet (EUV) and ion projection lithography, was reported at the Materials Research Society (MRS) conference in Boston recently. Hundreds of reports covered a wide range of innovative technologies, including MEMS, nanofabrication methods, organic semiconductors, optical devices, FRAMS, silicon carbide and gallium nitride devices.
Lenses for an EUV system for next-generation lithography have to be 10x smoother than the Hubble telescope, and they require 40-80 film layer pairs, each a quarter-wavelength thick, according to Sheila Vaidya, program leader at Lawrence Livermore National Laboratory. The lab is working with Veeco on a new sputtering system that can coat six lenses at once using ion beam sputtering rather than a magnetron to deposit molybdenum/silicon multilayers, each 240nm thick with precision of <0.1Å. Using a double-thick underlayer reduces the effect of any particles, she said.
No known material can protect an EUV x-ray mask from particles, so a thermophoretic approach is being investigated, Vaidya explained. Warmer, higher energy gas is pumped next to the mask. Initial work indicates that gas-particle collisions will drive particles away from the lens into the cooler ambient air. Experiments with DUV resists indicate 3x better sensitivity will be needed, and multilayer resists are being considered.
The current x-ray source, a xenon gas jet blasted by three laser beams, is unsatisfactory (too much x-ray emission is scattered, so that 10x better collection would be needed), and a number of other sources are being investigated. One approach is a capillary with differentially pumped xenon at about 1 torr. Cymer and some European firms are also working on alternate plasma sources, she said. The EUV program target is to achieve 70nm devices in production by 2005, and she indicated progress is on schedule.
Conventional novolac resists are too light-absorbent for 193nm, but a number of alternatives are in development, such as methacylates, according to Elsa Reichmantis, director at Lucent Technologies' Bell Labs polymer and organic materials research department. Alicyclics are being developed with high effective carbon content, minimizing structural oxygen. A number of alternatives being investigated include acrylate-doped alternating co-polymers, but acids or esters must be attached to aid solubility. Norbornyl chemistry offers large solubility when light changes the chains from acidic to esters. Inhibitors include cholate-based deionizers, which may be needed to prevent outgassing that could degrade optics, according to Reichmantis.
The problems are even tougher for 157nm resists because every known material absorbs this light. Fluorinated polymers and other novel polymer architectures are being explored to provide transparency, coupled with the needed solubility, sensitivity, contrast, etch resistance, purity, and shelf life, according to Reichmantis. Similar development will be needed for EUV resists.
Ion projection lithography for disk patterning
While making progress as a deep submicron exposure method in development by a European consortium, ion projection lithography is finding another use in disk patterning for the data storage industry.
As storage densities increase, nanopatterning of disk surface films is required. In July 2000, a two-year project began to develop ion projection disk patterning, involving IBM, Leica, IMS in Stuttgart, and the Fraunhofer Institute for Silicon Technology, Itzehoe, Germany, according to Wilhelm Bruenger of Fraunhofer. Spots for the nanopatterns are created by interference in cobalt/platinum multilayers.
The technique can pattern a small disk, about an inch, at one shot, according to Bruenger. Fraunhofer is now working on resist development for the process, and a new open stencil mask is being designed and fabricated for the project.
Amorphous diamond (a-D) may provide a more suitable material than silicon for surface micro-machined devices, suggested J. P. Sullivan and coresearchers from Sandia National Laboratories, Albuquerque, NM. Initially this material, formed by pulsed laser (248nm KrF) deposition on a graphite target in a 2-3 hour plasma process, was thought not to be promising because of excessive as-deposited internal stress (>7GPa). But it was discovered that annealing the film, consisting of four-fold and three-fold coordinated carbon, completely relieves this internal stress by converting some of the four-fold sites to three-fold. This takes only a couple of minutes at 600°C since only about 6% of four-fold sites have to be converted, according to Sullivan.
The material has many advantages over silicon, such as a naturally hydrophobic surface that resists stiction, chemical inertness, excellent wear resistance and high fracture strength, and biocompatibility. Unfortunately the fabrication process is line-of-sight so it cannot make conformal coatings. The masks used for poly-Si devices can't be used; sidewalls must be sloped. To overcome this drawback, the research group is now working on hybrid amorphous diamond and polysilicon structures that might take advantage of the large infrastructure available for silicon processing.
New input for 2001 Roadmap
The urgency of exploring innovative solutions to future processing and device problems was stressed in a talk by James Hutchby, director of nanostructure and integration sciences at Semiconductor Research Corp., Research Triangle Park, NC. After his talk, Hutchby said he is in the preliminary phases of organizing a global team to contribute to the 2001 International Technology Roadmap for Semiconductors (ITRS). This group would explore novel technology beyond current device structures and processing methods.
The current Roadmap, which runs into an increasing array of red barriers in the 2005 and later periods, indicating problems with no known solutions, is basically a linear progression, Hutchby suggested. It is based on using present CMOS processing methods and projecting them forward with new materials to solve problems in areas like interconnect and short channel effects (see figure on p. 32). An alternative approach would be to consider new device structures, such as dual gate CMOS and vertical MOSFETs. A third alternative would be to look at disruptive technologies that might displace current methods, like quantum dots and other nanotechnology concepts.
He pointed out that often in the past the industry has moved beyond limits with advancing technology, such as extending the use of optical lithography. He suggested that of what he identified as three main limits for CMOS — lithography patterning, device scaling, and interconnects — the interconnect problem will probably prove the toughest. The Roadmap suggests, for example, that the copper diffusion barrier must get thinner and thinner, and then go away. But no one knows how to prevent Cu electromigration without some barrier. As dimensions shrink, the impact of being off by only a few atoms in a process would have increasingly large effects on critical parameters. With scaling, device switching gets faster but interconnects get slower, and there are increasing levels of interconnect as more devices are packed on a chip.
Some researchers are already exploring microscale methods for developing devices that take advantage of tunneling effects, for example. Other work is looking at "smart" interconnects that would only link good cells. Computation methods are also being explored, such as systolic arrays that interact only with nearest neighbors. Optical devices, including guided wave as well as conventional light transmission methods, are also being researched.
Even processing techniques now considered too slow for production, such as molecular beam epitaxy, might eventually prove useful for future devices, Hutchby said. The new group he is organizing would add inputs on some of these promising research paths into the 2001 Roadmap process. — R.H.
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Motorola scientist receives award for molecular electronics research
Nami Choi, principal staff scientist at Motorola Labs, Tempe, AZ, has received a special award for development of probes for a scanning probe microscope with carbon nanotubes (CNTs). This award was issued by the Joint Research Center for Atom Technology (JRCAT), a Japanese government lab (http://www.jrcat.or.jp). Choi is assigned to the labs of JRCAT in Tsukuba, Japan, where she is working on a 10-year research program looking into atomic-level manipulation of matter.
 SEM image of the CNT-AFM tip. (Source: JRCAT) |
The goal of the JRCATs atom technology project is to establish a new paradigm for materials science by creating new atomic orders and nanostructures in space, on solid surfaces, or within bulk solids through the manipulation and control of atoms. Projects include the development of a synthetic technology to form silicon nanostructures <10nm, the identification and manipulation of chemical-biological species of atoms and molecules on a solid surface, and exploring new electronic materials and related physics for the development of atom technology.
Choi was recognized for her achievement in affixing a CNT to an atomic force microscope (AFM) probe tip (see photo), creating resolution enhancement at least three times better than that achieved with a conventional AFM. In a demonstration of the probe, Choi imaged DNA molecules that are ~3nm in diameter.
The research by the Motorola Labs scientist is expected to lead to higher resolution microscopic imaging in general, and in particular provide the opportunity to study DNA and other biological molecules in greater detail. In turn, this is expected to lead to a better understanding of the properties of molecules and how they function. As semiconductor devices continue to shrink and new nanometer-scale structures such as quantum dots and CNTs are being studied for use in future devices, the imaging of such objects will also require the high resolution provided by these probes. While there are no plans for commercialization at this time, the technique will be further refined. — P.B.
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Semicon Japan 2000: Technology updates amid upbeat forecast
There was more than enough technology on display and business to follow to keep over 120,000 people busy at Semicon Japan in December. The event opened with Semi's consensus forecast of an optimistic 22% growth (to $56.7 billion) in 2001 for the semiconductor equipment industry as technical sessions outlined new solutions to interconnect and other fab challenges.
Copper/low-k update
Copper deposition and low-k dielectric integration continued to be a topic of much debate. Takeshi Nogami, Sony Corp., provided a copper/ low-k status update, and described possible disruptive technologies, such as supercritical drying to create dielectrics with k values as low as 1.1.
 Figure 1. Three-dimensional structure of NEC's "triple damascene" interconnect. (Source: Semi, Semicon Japan 2000) |
Nogami's paper suggested WN and TiSiN as potential barrier materials to replace TaN, with one advantage for WN being that CMP is simpler because it uses the same slurry as Cu. Still, the copper/barrier interface, the key to electromigration resistance, is best with TaN. Another paper by Tetsuo Matsuda of Toshiba showed some experimental results with the message that care must be taken in understanding TaN barrier performance. A clever experiment showed that Cu diffusion through TaN into SiO2 is dramatically accelerated in trench structures. The thermal budget of subsequent processing must be manipulated carefully to minimize the effect.
Some novel interconnect approaches were presented, including NEC's "triple damascene" process. The main idea is to have two different thicknesses of the top layer of copper, which essentially creates three layers of copper. The benefit is that critical paths can get lower resistance with deeper instead of wider lines (Fig. 1). NEC claims a 30% reduction in wiring delay for critical paths and a possible 5% reduction in chip size for 130nm CMOS technology with this approach.
 Figure 2. TEL's spray coating process. (Source: Semi, Semicon Japan 2000) |
Tokyo Electron Limited's review of its low-k spin-on dielectrics included a look at an alternative spray coating system that could reduce the material used by 90% compared to spin coating (Fig. 2).
Fujitsu presented an etching scheme for a hybrid low-k/SiO2 dielectric structure. SiLK was the low-k material studied, and it was used as the intra-layer dielectric for electrical performance considerations. SiO2 is the inter-layer dielectric, which allows for better heat dissipation and a more reliable damascene structure. Etching of SiO2 is the critical step, and this is accomplished with a dual hard mask structure of SiN/SiO2 and a C5H8/Ar/O2 gas mixture.
A close look at thin gate oxides
A collaboration between the University of Tokyo and Toshiba shed some new light on gate oxide breakdown. The researchers looked at much of the data reported in the literature and found that the usual Weibull distribution does not describe the time to breakdown for ultra-thin oxides. As shown in Fig. 3a, the data matches the expected linear relationship for 3.4nm and 5.9nm oxides, but the data for 1.8nm thick oxides does not follow the trend. They found this in several published works, and they discovered that for oxides in this thickness regime, a lognormal plot (Fig. 3b) is a better fit. The implication of this difference in the statistical description is that the limit on the smallest oxide thickness might be determined by the worst leakage current due to thickness inhomogeneity. The apparently increased importance of homogeneity is another bit of evidence that atomic layer processes will be critical here.
Flash memory fabrication
Flash memory, the only product type with a whole session devoted to it at Semicon Japan, presents some challenges to wafer fabs, and both Tokyo Electron Limited and Applied Materials had something to say about it.
Tomohiro Ohta of TEL emphasized the need for environmental control, noting that there can be significant problems if a DRAM line is shifted to flash memory production. Tunnel oxide formation and other critical steps in flash memory production are more susceptible than DRAMs to factors like organic contaminants. One tool from TEL that addresses the unique demands of flash memory is a vertical furnace with in situ ozone cleaning for removing adsorbed organic contaminants. Ohta also discussed an oxide/nitride/oxide (ONO) in situ sequential process for interpoly dielectrics. Performing the three processes without the loading/unloading steps reduces contaminants and improves throughput. Applied Materials also presented results of its ONO consecutive deposition process, citing uniformity advantages of a single-wafer multichamber LPCVD tool.
APC and e-diagnostics
One session of the technical symposium was titled "Fusion of Manufacturing Science and Information Technology," and this was quite an appropriate description of the work being done to tie together advanced process control (APC) progress and the current developments in e-diagnostics. E-diagnostics might not be worth the trouble if the data transmitted out of the equipment does not give a detailed picture of what is happening in real time. Therefore, the success of e-diagnostics depends on APC.
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One example given for the kind of APC that will facilitate e-diagnostics included refinements of optical emission spectroscopy (OES) and impedance monitoring (IM) in plasma etchers. Nobuo Tsumaki of Hitachi explained that more accurate endpoint detection can be achieved by using multiple wavelengths of plasma emission. For IM, a good circuit model is critical. These real-time monitoring techniques are important for e-diagnostic control of etching processes.
Another article from Hitachi described a real-time dark-field inspection tool for classification of defects and particles.
It differentiates between particles and scratches by using the difference between light scattered by convex and concave defects. It was shown to be 87% as effective as off-line SEM reviews of such defects. This will enable real-time control of defects resulting from the CMP process.
Intel and Selete had papers emphasizing the importance of international standards for any successful industry thrust in e-diagnostics. Shigeru Kobayashi, a Hitachi assignee to Selete, said, "International consensus development is mandatory and should be driven by international consortia."
David Bloss of Intel reviewed the recent guidelines put out by International Sematech and had some additional recommendations. Given the time that it takes to develop standards, Bloss said that it will be critical to create standards in a "non-sequential manner" so that prototypes can be produced while the development continues, thus accelerating the process. Another key strategy will be to adopt proven standards from outside the IC industry where possible. This will also reduce the total time, investment, and risk for the industry.
 Figure 4. Agilent's port scalability scheme for SOC test. (Source: Semi, Semicon Japan 2000) |
SOC test approaches
In the area of test, much of the talk focused on the challenges of system-on-chip (SOC) test. The difficulty of testing the varied technologies found on an SOC has been one of the stumbling blocks frequently cited for the limited adoption (so far) of SOCs. Yokogawa Electric Corp. and Agilent Technologies each proposed solutions.
Muneo Ishinohachi, chief technical manager at Yokogawa, proposed a two-prong approach to reduce the cost of SOC test. A high-end mixed signal tester should be used during the test program development phase, but in production, not all of that functionality is needed for test. Yokogawa's solution is to add some selected measurement functions to a basic tester so that only as much horsepower as needed is being implemented for production SOC test. Masaharu Goto of Agilent's Silicon System Test Division described a different approach in his paper. Agilent has created what it calls "port scalability," where selected test pins are run at higher frequencies, while the remainder run simultaneously at lower frequencies (Fig. 4). This makes for a cost-effective solution for the large majority of SOCs, where a relatively small number of signals operate at high frequencies. Like Yokogawa's approach, this prevents the user from paying for unnecessary test capability. — J.D.
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"(Micro)Spring is coming"
FormFactor has licensed its wafer-level packaging and test processes to Germany's Infineon Technologies AG. In the deal, Infineon will have a worldwide license to use FormFactor's MicroSpring contact technology for use in chip assembly as well as in test and burn-in procedures. Infineon, which also invested $5 million in FormFactor, says the technology will simplify its manufacturing and reduce back-end process costs, and plans to use it with 300mm wafers. On p. 78, John Novitsky and Chuck Miller of FormFactor discuss a technique for attaching wafer-level test and interconnect contacts with a wire bonder.
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Is IBM the 130nm-process leader?
Dubbing it "CMOS 9S," IBM has released a few details about its "most advanced, 130nm process technology." This is the first combination for production of copper wiring, silicon-on-insulator (SOI) transistors, and low-k dielectrics. As one benchmark, this technology enables fabrication of the smallest SRAM memory cell in production — 2.16µm2, which allows for more high-performance memory to be placed directly onto a chip, resulting in faster, more efficient processors.
IBM is producing a variety of chips using the CMOS 9S process on a pilot production line in its Semiconductor R&D Center in East Fishkill, NY. It will introduce the technology on its high-volume Burlington, VT, manufacturing lines, for first customer shipment early this year. This new manufacturing technique will be used to produce future generations of the IBM POWER4 processor, which will ship next year in a next-generation IBM eServer, codenamed "Regatta."
Bijan Davari, IBM Fellow and VP of technology and emerging products for IBM, said, "Our new chipmaking recipe integrates more complex, high-performance ingredients onto a chip than ever before. This unique technology can help meet exploding customer demand for higher performance, higher function products. The integration of silicon-on-insulator, copper and low-k insulation offers a powerful combination of technologies that maintains our two-to three-year technological lead."
 IBM's CMOS 9S 130nm IC fabrication technology. (Source: IBM Microelectronics) |
CMOS 9S takes advantage of the performance benefits of SOI (see SEM), which dramatically improves transistor performance up to 35%. According to Andrew Allison, editor and publisher of Inside the New Computer Industry (http://aallison.com), "In the race to 130nm technology, IBM's proprietary 9S process brings shorter gate lengths, nine metal layers and SOI, which by itself provides a 20% to 35% performance boost to the party. Advanced processors are not just about performance and density. Chips based on such processors are likely to dominate the battery-powered market as components are optimized for battery size and life." By boosting chip performance and reducing chip power requirements, SOI is critical for chips that will power a wide range of products, such as Internet servers or wireless communications gear.
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Allison views claims being made for 130nm capability with some skepticism because the standard polysilicon gate channel length needed to take full advantage of 130nm is 65-70nm for disclosed 130nm and about 50nm for short-channel devices. "This ratio is considerably less than for older processes. Unfortunately, even knowing the real dimensions of the process isn't enough," says Allison. Tabulating his view of the status of 130nm IC fabrication technology (see table), Allison says, "The substrate, effective dielectric constant, and number of metal layers all have significant impacts on performance."
Allison claims, "Given that Intel won't begin to use copper and low-k until the 130nm generation, and remains in denial about SOI, while IBM has been in production with copper for three years, Intel's claims of 130nm process leadership are ridiculous on their face. The multiple-source foundry process (see TSMC in table) is at least as capable as Intel's, and IBM's proprietary 9S process is clearly more advanced. I estimate that IBM's process technology, which integrates SOI, Cu, and low-k dielectric, is as much as two to three years ahead of Intel's at present." — P.B.