The search continues for high-k gate dielectrics
02/01/2001
— Jeffrey C. Demmin, Senior Technical Editor
The 46th annual IEEE International Electron Devices Meeting provided the industry with the latest updates on a variety of technical advances in semiconductor processing, but high-k dielectric discussions drew particular attention during the recent San Francisco event, as the processing area is proving to be a significant challenge on the International Technology Roadmap for Semiconductors (ITRS).
Zirconium, hafnium oxides
Many of the talks about high-k gate dielectrics focused on the latest developments with Zr and Hf oxides. Three papers from the University of Texas (UT) at Austin explored various characteristics of HfO2, one of the better candidate materials because of the possibility of direct insertion into standard CMOS process flows.
S.J. Lee and co-workers at the University of Texas and Schumacher demonstrated a 10.4Å equivalent oxide thickness (EOT) HfO2 film created with an in situ rapid thermal CVD process. Good thermal stability of HfO2 was reported by Laegu Kang et al., with no interface layer forming between the HfO2 layer and the poly-Si gate (Fig. 1).
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Figure 1. HfO2 gate dielectric and interface layer a) after dopant activation, b) after 900°C/1 min RTA, and c) after 1000°C/1 min RTA. (Source: IEDM)
The formation of an interface layer has been an issue because it increases the EOT during post-deposition thermal processes. Another UT team reported on scalability below 10Å EOT with a TaN gate electrode. In that paper, presented by Byoung Hun Lee et al., an 8Å layer was reported, with the replacement of a poly-Si gate by TaN to avoid the poly depletion effect. They claim that this technology can be extended to the 50nm technology node on the ITRS, but they do say that much work remains.
Other materials
Silicates were also discussed as an option for high-k gate dielectrics, and one new material reported was a Si-doped zirconium aluminate (Zr-Al-Si-O). With TiN gates, this material remains amorphous at the high temperatures of CMOS processing (unlike ZrO2 and HfO2), so replacement gate processing is not needed. L. Manchanda et al. of Lucent Technologies' Bell Labs reported on a 12Å EOT Zr-Al-Si-O film with leakage current <50mA/cm2 at 1V.
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Figure 2. IBM's integration of an ultra-thin AlsO3 gate dielectric makes it a candidate for 100nm technology. (Source: IEDM)
Another dielectric that stays amorphous at CMOS processing temperatures is AlsO3, although some believe that this is not a long-term solution because of a relatively low dielectric constant (~10). Still, a team from IBM demonstrated integration of an ultra-thin AlsO3 dielectric in an 80nm nFET with a poly-Si gate. The 10-15Å EOT alumina (see Figure 2) was deposited with atomic layer CVD, and the authors (D.A. Buchanan et al.) suggest that this technology could be an effective approach at the 100nm node. A remaining challenge for the authors is a reduction in mobility due to fixed charge.
Perhaps the most intriguing paper at the IEDM conference was from H.J. Osten et al. of IHP in Germany. This team reported on high-k gate dielectrics based on praseodymium oxide (Pr2O3). They demonstrated 14Å EOT, k=31, good reliability, no degradation of electrical properties after 1000°C/15sec anneals. Most significantly, they demonstrated leakage current of 5nA/cm2 at 1V. This result is about four orders of magnitude lower than the best reported results for other high-k materials.
When will high-k be ready?
A general trend in these talks about high-k gate dielectrics was that significant advances are being made, but fundamental challenges persist. In an interview at IEDM, Ludo DeFerm of IMEC — the Belgian research organization with multiple papers at the event — was not optimistic about high-k dielectrics being available in time for 100nm technology. DeFerm, VP of business development at IMEC, believes that it is not yet proven that there is a scalable material that fits the criteria for high-k gate dielectrics. Interface issues with silicon, hot carrier reliability issues, deposition methods, and resistance to high-temperature processing make high-k integration in production unlikely until 70nm, according to DeFerm.
The industry's concern with high-k gate dielectrics is reflected in the efforts to continue improving the scaling performance of oxides, by nitridation for example. Paul Nicollian et al. of Texas Instruments discussed a nitridation scheme that decreases the EOT by approximately 6Å. By exposing oxides to nitrogen plasma, a relatively high concentration of nitrogen can result without the negative effects of hydrogen associated with other nitridation processes. The resulting remote plasma nitrided oxide (RPNO) has a lower leakage current because the nitrogen allows the film to be thicker for a given EOT.
 Figure 3. Cross-section of a 40nm gate length MOS transistor from AMD with a nitride/oxynitride stack gate. (Source: IEDM) |
Work also continues on improving the reliability of SiO2 as a gate dielectric. Several papers addressed the subtleties of using deuterium instead of hydrogen in some of the processing. Yuichiro Mitani et al. of Toshiba demonstrated that the suppression of trap creation is improved significantly by deuterium pyrogenic oxidation and poly-Si deposition using SiD4 instead of SiH4. They showed that the effectiveness of deuterium at suppressing trap creation depends on the method of deuterium incorporation. Their process flow was better than deuterium annealing, which they concluded was because the annealing process leaves most of the deuterium at the Si/SiO2 interface, while the pyrogenic oxide leaves deuterium throughout the film (Fig. 4). A paper from Lucent Technologies' Bell Labs and the University of Udine in Italy gave some related information on deuterium effects. David Esseni et al. showed that deuterium annealing affects the generation of Si/SiO2 interface states, but only at large Vg. They also showed that stress-induced leakage current (SILC), a bulk oxide effect, is not isotope dependent for annealing processes.
Stacked films are also being used for gate dielectrics.
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Qi Xiang et al. of AMD and Stanford described a 12Å EOT nitride/oxynitride (N/O) stack gate in a 40nm CMOS device (Fig. 3). A benefit of the N/O stack gate is its resistance to boron penetration, which allows for pre-doping of poly-Si gates to minimize poly depletion. The stack is created with thermally grown oxynitride followed by Si3N4 deposition. The second step is required because with the oxynitride only, there is not enough nitrogen incorporation in the film to resist boron penetration.
Figure 4. SIMS profile of deuterium pyrogenic oxide and deuterium annealed oxide, which shows deuterium primarily at the SiO2/Si interface for the annealing process. The more uniform distribution of deuterium with the pyrogenic oxide allows it to suppress trap creation more effectively. (Source: IEDM)
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E-commerce for designers
The highly technical nature of the audience at IEDM makes it a premier venue for EDA tool vendors. One intriguing approach came from the startup e*ECAD. For a few months, the company has been offering access to a set of EDA tools, with the users being charged only for the time that they use them. This concept provides an alternative to a high licensing fee that is the standard industry billing system and is especially appealing to small design firms. A small company can use a tool as it needs it, or try out a new tool without a large investment. There are also some bells and whistles that allow, for example, tracking of the time that each designer has used a tool.
Distribution of design tools over the Internet seems like a good application of e-commerce. With an essentially intangible product that gets updated frequently, it makes a lot of sense to be able to receive the product when you want it via the Internet. (See Industry Insights on p. 152 for some thoughts why e-commerce might not work for semiconductor capital equipment.)
There are some significant concerns from both users and suppliers about this approach though. The ability to track usage so precisely could raise issues about monitoring something that appears to be — but may not be — a reflection of the productivity of different employees. A new approach like this also might have a hard time fitting into traditional budgeting categories. On the supplier side, the tool vendors signed up to supply tools this way are relatively small players. Larger vendors might be reluctant to distribute their tools through another party, which is part of the widespread e-commerce challenge of maintaining brand identity when a third party facilitator is in the loop.
Still, the mavericks in the design world might jump on this chance to use more tools in a reasonably cost-effective manner. Richard Siemiatkowski, e*ECAD's president, also pointed out a nice feature of e*CAD's business model — its cash flow starts immediately with usage of the product. With virtually no leadtime in its delivery cycle, the business should avoid some of the inventory and distribution pitfalls that have plagued other e-commerce firms. — J.D.
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 Figure 1. Intel's 30nm gate length device fabricated with conventional planar CMOS technology. (Source: IEDM) |
Mano a mano at sub-50nm
No IEDM would be complete without a session for the battle of the smallest device features. You could probably guess most of the entrants without looking. Intel, NEC, Bell Labs, Infineon, UC Berkeley, and Stanford populated the list.
Intel checked in with a 30nm gate length (corresponding to the 70nm technology node), achieved with a conventional planar CMOS process flow (Fig. 1). This was accomplished with what Robert Chau et al. of Intel referred to as "aggressive scaling" in its paper. The process included a standard two-mask phase shift mask using 248nm lithography with overexposure. The physical gate oxide thickness was below 10Å, and the gate electrode was poly-Si. The authors were optimistic that this proof of 70nm technology with a conventional CMOS approach meant that only evolutionary developments will be needed to get to that node.
 Figure 2. A polysilicon V-gate technology from Bell Labs was created with current production tools and without lithographic control of critical dimensions. (Source: IEDM) |
NEC's team (H. Wakabayashi et al.) discussed MOSFETs with gate lengths of 24-45nm, facilitated by high-ramp-rate spike annealing to reduce thermal budgets. A ramp-up of 300°C/sec and ramp-down of 100°C/sec were achieved.
Jakub Kedzierski et al. of the University of California at Berkeley and the Lawrence Berkeley National Laboratory demonstrated a 15nm gate length MOSFET with PtSi and ErSi1.7 source/drains for PMOS and NMOS, respectively. The silicides reduce both the leakage current and the series resistance, making this approach a promising technology for the sub-50nm regime.
 Figure 3. Infineon's vertical double gate MOSFET. (Source: IEDM) |
Other approaches presented used novel structures for their small-feature achievements. C.-P. Chang et al. of Bell Labs showed a V-gate structure (Fig. 2) with gate critical dimensions that are insensitive to lithography and etch profile variation, making the approach a good candidate for long-term scalability below 50nm.
Infineon Technologies and Bell Labs demonstrated vertical structures. Thomas Schulz et al. of Infineon presented data on vertical sidewall transistors (Fig. 3) with channel lengths down to 50nm. Sang-Hyun Oh and co-workers — 37 of them — from Bell Labs and Stanford demonstrated the first p-channel 50nm vertical replacement gate (VRG) MOSFET. One innovation in this device was the use of ion implantation for channel doping, which is important for vertical channel engineering. As with other vertical technologies, the key feature for scalability is the non-lithographic control of critical dimensions. — J.D.