At long last, SOI wafer market on the move
02/01/2001
Takashi Ogawa, Gartner Dataquest, San Jose, CA
Silicon-on-insulator (SOI) technology has a three-decade history, constantly creating the hope of enabling technology for next-generation, high-speed, or low-power-consumption devices. Once hobbled by high material costs, SOI technology commercialization is moving toward reality, but a key business issue remains: When and how will device manufacturers commercially introduce SOI technology?
The SOI wafer forecast
Gartner Dataquest expects total SOI wafer demand will grow by a compound annual growth rate (CAGR) of 55% between 1999 and 2005; then the demand will reach 187 million square inches (MSI) in 2005 (Fig. 1). SOI wafer demand grew to 13.8 MSI in 1999, up 37% from the previous year (Fig. 2).
 Figure 1. Total SOI demand will reach 187 MSI in 2005, with communications and data processing devices driving high demand for thin film SOI wafers. |
The principal driver of SOI device demand will gradually shift from traditional military/aerospace and industrial equipment to data processing, communications, and consumer electronics areas, which will accelerate very thin and thin film SOI wafer demand.
Wafer prices will follow the learning curve according to the evolution and demand for SOI wafer production technology; 200mm wafer prices will drop sharply, and the average price of thin film SOI wafers will fall below the level equivalent to four times that of the ordinary bulk wafer in 2004. Based on this assumption, the total SOI wafer market will reach $1068 million in 2005, with a CAGR of 48% between 1999 and 2005 (Fig. 3).
Growth through thick and thin
Mainstream SOI wafer demand has shifted from thick film to thin film technology. While the former mainly consists of high-voltage and high-temperature devices used for military, industrial, and aerospace applications, the latter is used to fabricate high-speed/low-power-consuming devices popular for data processing and communications applications. In fact, the share of the thick film segment in the SOI wafer market dropped from 80% in 1995 to 53% in 1999 and was taken over by the thin film segment (see Fig. 2). In recent years, demand has been clearly diverted from military/aerospace and industrial applications to consumer electronics, which accompanies the demand shift to thin film (buried oxide layer of 1µm or less) and ultrathin film (0.15µm or less).
 Figure 2. Once dominating overall SOI demand, thick film SOI demand is now rivaled by demand for thin film SOI. |
Gartner Dataquest expects that thin film SOI wafer demand will achieve a 63% CAGR by 2005, reaching 124 MSI, and will by far dominate overall SOI demand. Similarly, thick film SOI wafer demand will be driven by industrial and automotive applications, such as high-voltage and high-temperature devices, in addition to traditional military and aerospace applications. Thus, the CAGR between 1995 and 2005 will be 43%, and total demand will reach 63 MSI in 2005.
Finally, attention is turned to the wafer market on a value basis, which will be governed by price trends. Gartner Dataquest's SOI wafer market survey states average prices vary greatly according to the manufacturing method, shipment volume, and other factors. This is particularly true in thin film wafers. The average price of a 200mm wafer in 1999, for instance, varied between $300 and $800. With such price variation, the average price will decline significantly as demand growth drives cost reduction. On the other hand, the average price of a thick film SOI wafer made by the bonding method will not face a sharp decline but will follow a gradual downward path for the next five years.
The acceleration phase
Since 1997, two major moves in SOI development have portended major changes. First came the advent of high-performance and cost-effective SOI wafer production technologies, such as SOITEC's Smart Cut and Canon's ELTRAN processes. Second, IBM successfully developed SOI devices and started volume production for captive consumption. IBM implemented SOI technology in the production of the PowerPC, which started in the middle of 1999. The company plans to expand the application to standard products for servers and mainframes, followed by ASICs fabricated on SOI wafers. It will use captive SOI wafer supplies for the time being, but will likely use outside sources as demand grows. IBM's move spurred many devicemakers to launch their own development and commercialization efforts. In particular, Motorola, Texas Instruments, Mitsubishi Electric, Fujitsu, and Samsung are working on high-speed and low-power- consumption devices using thin film SOI technology.
 Figure 3. In 2005, the SOI wafer market will grow to be a $1068 million business, 10 times its size in 1999. |
SOI technology is increasingly finding new applications, such as high-temperature, high-voltage, or smart power devices. For instance, Philips, which focuses on high-voltage SOI devices, and Honeywell, which works with high-temperature SOI devices for automotive and aerospace uses, are leaders in new applications. Most recently, new frontiers have been explored, such as SOI sensors using micromachining technology and miniature displays implemented on the SOI substrate.
SOI development initiatives, from commercial production to long-term applications research, have been rampant recently. As a result, SOI wafer demand has grown significantly, albeit not in the same volumes as the traditional polished wafer market. Clearly, the market gained momentum with surges in SOI technology development activities. Although it suffered a temporary setback in 1997 because of the stagnated semiconductor market, resulting in a 10% decline, the market exploded at 31% ($65 million) in 1998, fueled by IBM's initial activity. In 1999, the SOI merchant wafer market registered 56% growth and reached $100 million.
Dataquest's perspective
In 1998, the SOI wafer market entered a full growth phase. From the production cost point of view, however, full pervasiveness of SOI technology has to clear a number of hurdles. First, the issue of substrate floating must be addressed in circuit design. There is the choice between full or partial depletion devices, which is under consideration by vendors. IBM seems to have selected the partial depletion design, but it has still to agree on the advantages of an SOI device.
The future SOI wafer market will be largely affected by continued innovation.
It is important to recognize that material technology, as well as cost reduction, will play a crucial role in market expansion. As seen in IBM's development record, the breakthrough in material technology has been contributing greatly to the commercialization of SOI devices. This means the future business style for SOI wafers will be different in various aspects from that for the traditional wafer.
Wafer technology and its application will vary greatly among customers, necessitating a high degree of customization. Also, because material design is directly related to device structure and characteristics, SOI wafer material suppliers are expected to participate in the process design at earlier stages.
These moves point to new value-added opportunities for the wafer business. Vendors specializing in SOI wafers — such as SOITEC and Ibis — are involved in joint development efforts for SOI device technology not only with wafer suppliers but with devicemakers as well. In the SOI wafer age, Gartner Dataquest believes that wafer suppliers will increasingly assume a role of process provider, particularly for SOI materials.
Takashi Ogawa is a principal analyst at Gartner Dataquest, based in Japan. He can be reached at ph 81 3-3481-3612, fax 81 3-3481-3645, and email [email protected], Gartner Interactive http://www.gartner.com. This article is based on the report, "SOI Wafer Market Forecast Update: The Market Is on the Move," which is one update in a series of reports analyzing the emerging SOI market. This report, available from Dataquest, is $795.
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Further evolution of SOI wafer technology
A new manufacturing technology is attracting attention for its capability to significantly reduce wafer production costs while ensuring high-quality (low defect level) SOI wafers.
In the new SOI manufacturing method, two silicon wafers are bonded, and the SOI layer is formed. Then either silicon layer is peeled off and recycled for a new process. A conceptual view of this wafer recycling process is shown in the figure.
 Source: Gartner Dataquest |
The process starts when Wafer B (serving as a base wafer) is bonded to Wafer A, which is treated to form a device active layer and an oxidized layer. Then Wafer A is peeled off, and the base wafer with the SOI layer is treated to complete an SOI wafer after a final treatment. Significant cost reduction can be realized by recycling the wafer that was peeled off from the bonded wafer. SOITEC, Canon, and Silicon Genesis, all of which use proprietary processes, have already implemented the manufacturing technique based on the concept.
Based on the wafer recycling process, these manufacturing techniques have some common elements: the methods for formation and treatment of the device active layer and the peeled layer on the donor wafer (Wafer A), and the method for peeling off the donor wafer after the bonding and formation of the SOI layer. Using these techniques as key elements, various vendors have completed their own process technologies.
SOI wafer technology is undergoing a much faster pace of development than material engineering, which is generally characterized by a relatively slow rate of technological evolution. The vigorous efforts are expected to help make breakthroughs in quality improvement and cost reduction, both of which will have a major impact on the emerging SOI market.