Issue



Wafer-level CSP, wafer-level assembly/test: Integrating backend processes


02/01/2001







John Novitsky, Chuck Miller, FormFactor Inc., Livermore, California

overview
A new technique using contacts applied by a wire bonder enables a wafer-level assembly and test approach throughout the entire final manufacturing process. This allows the traditional semiconductor backend to take full advantage of the economies of wafer processing found in the frontend. A key part of this is the resilient contact that can serve as both the test interface and the interconnection for first-level assembly.


Figure 1. Cross section of a MicroSpring contact fabricated on silicon wafers.
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In order for Moore's Law type of scaling benefits to apply to the backend of semiconductor manufacturing, an integrated wafer-level package process must exist, and it must include test, burn-in, and handling methods at the wafer level. While dozens of alternative wafer-level packages have been described, nearly all fail to address the wafer-level test and burn-in issues.

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Figure 2. Top view of a whole wafer covered with approximately 26,000 contacts. Tip accuracy is about ±38µm (x, y, or z) across the entire wafer.

A new approach integrates wafer-level chip scale packaging (CSP) fabrication, whole-wafer test, and final assembly. The core technology is based on fabricating MicroSpring contacts directly onto a wafer. These contacts, which have been used extensively in high-parallelism probe cards at over 25 IC fabs or test facilities, are used as a compliant and resilient interface to the whole-wafer contactors used at burn-in and then at test. They are also used as the first-level interconnect, either soldering or socketing the die to other substrates. After these contacts are fabricated on wafers, they allow a novel test method for whole-wafer long-cycle test, at-speed test at the wafer level, and a test method for singulated die.

Why wafer-level processing?
Wafer-level packaging and test can provide dramatic economic benefits for wafers that have modest to high yields, or for die that go through frequent die shrinks (hence delivering the desired but elusive scalability in the semiconductor backend). However, wafer-level packaging is a poor choice for die with low yields (few good die/wafer), as is whole-wafer testing. For users requiring an I/O fan-out on an area larger than the actual die, all wafer-based approaches are eliminated from consideration.

Approaches to wafer-level processing
There are more than 20 wafer-level CSP techniques being proposed or practiced, and more than 60 singulated CSP approaches [1]. Unfortunately, rather little consideration has been given to whole-wafer testing. Yet without an effective and economical whole-wafer test method, any wafer-level package approach fails the crucial test for a wafer-based process — scalability.


Close-up of MicroSpring contacts attached to a redistribution layer over the die.
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FormFactor's approach integrates the needs of wafer-scale CSP and of whole-wafer testing. Instead of building a wafer full of solder balls, which then requires tens of thousands of contacts to mate repeatedly and reliably at test, this approach is used to fabricate a compliant and resilient test contact on the wafer, use it as the test interface, and then use that contact as the final package interconnect. The benefits to this approach include:

  • low-cost wafer-level package fabrication;
  • simple whole-wafer test, with reduced challenges related to registration, co-planarity, etc.;
  • enhanced yields due to the elimination of tester guardbands resulting from the parasitics of traditional test sockets and fixturing;
  • improved package-to-board reliability because the spring decouples the CTE mismatch between the Si die and the substrate; and
  • improved electrical performance with the MicroSpring structure.

Fabrication of contacts onto wafers
Once the ICs on a wafer have been "probed" (and possibly have had laser repair and re-probe performed), these probed wafers are then delivered to a MicroSpring contact fabrication facility, which may be in the IC fab or elsewhere. The facility contains:

  • lithography equipment, used to build a redistribution layer of interconnect on the wafer;
  • wire bonders, used to bond contact "skeletons" onto the wafers; and
  • electroplating lines, used to build up the skeleton into a compliant and resilient contact.


Figure 3. Top view of a die with MicroSpring contacts. Note the very large power and ground planes, as well as the impedance-matched and path-length-matched signal lines.
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The process used to create a wafer full of contacts is as follows. First, an optional redistribution layer can be added to the wafer. This layer's primary purpose is to define the pads in the appropriate location for the assembled end-use stack-up. The structure of this layer is similar to those commonly in use today (i.e., polyimide and a metal trace). Next, a 25µm dia. Au wire is thermosonically attached to the pad. This wire forms the skeleton of the eventual contact. Wire bonding was selected as the means of beam forming because the possible shapes are essentially infinite, and the set-up times and costs are very low. Also, the industry maturity in wire bonding is high, which contributes to very high yields and low costs. Next, the wafer is electroplated in Ni alloys and finished with Au. The Ni alloys provide the strength, while the Au finish coat provides long-term resistance to oxidation.

These contacts embody the following "typical" characteristics (although essentially infinite variations are possible by designing a spring contact for each application):

  • height, 625µm;
  • contact diameter, 55µm;
  • tip diameter, ~75µm;
  • compression during test, ~125µm;
  • length of scrub, ~75µm;
  • compression force required, <80mg/µm of compression;
  • inductance, <1nH; and
  • minimum pitch, <500µm.

Figure 1 shows a cross section of a contact fabricated on silicon. Figure 2 shows the top view of a wafer covered with approximately 26,000 MicroSpring contacts. A top view of a single die with MicroSpring contacts is shown in Fig. 3, illustrating large power and ground planes, and tuned or balanced signal lines where required. Figure 4 is a side view of this die, demonstrating how the contact functions as a compliant test contact.


Figure 4. Side view of contacts on a die. Note that the cantilever and beam contact shape provides the compliance to the contact when used as the tester interface.
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Wafer-level CSPs have been created for die with lead-on-center (LOC) pads and die with peripheral pads. The wire bonds have been built directly over active areas, as shown in Figs. 3 and 4, with no problem being observed. These thermosonic ball bonds are formed/attached with approximately one-fourth of the typical energy required in conventional wire-bond assembly. The reduced energy and the extra polyimide layer are thought to eliminate the potential issues traditionally feared with bonding over active Si. Although the gold wire is bonded to the pad with a fraction of the normal energy, electroplating the wire and the ball bond results in a structure with roughly four times the area of a conventional ball bond. This increased area results in a typical pull-strength of ~70g and a typical peel strength of ~300g. These numbers are perhaps an order of magnitude stronger than those of conventional wire bonds.

Pre-production fabrication yields are already running above 98% at the whole-wafer level. In mature production lines, yields exceeding 99% are expected, which is about the same as traditional wire-bond assembly yields.

Testing wafer-level packaged ICs
There are two approaches to testing the packaged ICs with the technology described here. A technique for testing at the wafer level is being developed for the largest benefit in cost reduction and scalability. Another technique for testing singulated die is also being developed for purposes of compatibility with existing CSP handlers, test equipment, and process flows.


Figure 5. A whole-wafer cassette-clamping system for burn-in. The wafer is inside, and the edges of the whole-wafer contactor are protruding from the sides.
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For broadside wafer-level burn-in and low-speed/long-cycle test, (where "broadside" means that all of the I/Os on all of the ICs get tested simultaneously), a whole-wafer contactor has been developed with a wafer-level clamping system, as shown in Fig. 5 [2]. This system is being developed to fit in commercial burn-in ovens. The gold contact wipes on a gold pad on the contactor board. Registration issues are minimized, due to the fact that the contact tip is a sphere approximately 75µm wide, and this wipes on a pad that is about 700µm x 700µm (Fig. 6). The contactor is made of a low-cost material that also has a low dielectric constant and is reasonably matched to the CTE of the silicon wafer. The whole-wafer cassette pictured in Fig. 5 eliminates burn-in sockets, loaders, and unloaders for these burn-in sockets, and trays or tubes for the ICs. It also reduces the number of burn-in ovens required. It simplifies the interface issues, eliminating the need for a compliant burn-in contact undergoing thousands of burn-in cycles.

Whole-wafer testing can also increase the number of learning cycles possible over an IC product's lifetime. Wafer-based processes may result in test feedback becoming available a few weeks earlier than is typically practiced with singulated package assembly and test. For ICs with production lifetimes of only six months, this approach may result in several additional learning cycles, producing increased yields and higher profits for each wafer start.


Figure 6. The scrub mark of the contact on the test contactor pad is quite small, demonstrating dimensional stability and minimal registration issues.
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For at-speed testing at the wafer level, a new version of a multiple-DUT (device under test) head for a probe card is available (Fig. 7). The "pads" on this probe card are actually posts that are tall enough not to crush the non-DUT contacts when the test head is mated to the wafer. The number of channels present on the tester limits the number of DUTs. When the tip size, the positional accuracy, registration issues across an entire wafer, and other contributions are summed up, one can see that the target represented by the posts provides for a large margin of error, enhancing robustness for high-volume manufacturing.

Since most IC manufacturers today lack the whole-wafer handlers and equipment in their backend test and package assembly operations, FormFactor has been developing a test flow compatible with singulated CSP handlers, burn-in boards, etc., which most IC manufacturers do have. It involves bringing up a "socket" for a singulated die with MicroSpring contacts (Fig. 8). This is a radically simplified socket compared to conventional CSP test sockets. It is merely an x-y registration frame, with a lid to apply backside pressure to the die. The socket does not contain expensive or problematic components such as compliant pins or coaxial contacts. The electrical parasitic values of the CSP socket are eliminated; die registration issues are simplified; and the mechanical or cleaning issues associated with compliant test pins are eliminated. Versions are being developed for both automated loading/unloading and manual operation (for use in the early stages of silicon verification). The singulated ICs are shipped in JEDEC trays, and they are stored/picked in either "live-bug" or "dead-bug" style.

Permanent or socketed assembly
There are three methods to assemble these ICs to substrates. They can be soldered, attached using conductive epoxies, or socketed. The socketed approach has been termed self-socketing die (SSD).

Surface mounting die with MicroSpring contacts to PCBs uses conventional surface mount techniques. The paste is stencil-printed onto the PCB (typically around 150µm deep on a 300µm pad); the die are picked out of JEDEC standard trays; the contacts are pushed into the paste; and the solder is reflowed in conventional reflow ovens (Fig. 9a). Underfill is not recommended, reducing costs, allowing the wafer-level package to vent, and making module repair (die removal) straightforward if it is needed. An epoxy "dot"/standoff is recommended to prevent damage due to mishandling and to improve the shock and vibration reliability test results (Fig. 9b).

Over a dozen different configurations of Rambus RIMM modules, SODIMMs, and DIMMs have been produced with this technology, and they have been subjected to a battery of reliability tests [3]. Fundamentally, the contact decouples the CTE mismatch between the Si die and the PCB. For example, the two-sided module shown in Fig. 9b typically survives 3000-5000 thermal shock cycles, Condition B (-55 to 125°C, 5-min dwell times, <10-sec transition times), liquid to liquid, before the PCB begins to fall apart. Note that this is performed with no underfill, and with no mechanical lid holding the die in place. In addition, no prebake of the die is performed, and the assembled modules still deliver outstanding reliability results. (The package is probably JEDEC Level 1 with respect to moisture preconditioning, but more data is needed to verify this.)

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Figure 8. (below) Burn-in and test socket for die with MicroSpring contacts. (Photo courtesy of Yamaichi)

As shown in Fig. 9a, the top of the solder is typically at least 375µm from the die surface, which is typically covered by two passivation layers, the first put on by the IC manufacturer, and the second as part of the redistribution layer. These factors contribute to a reduction of expected alpha-particle-induced soft errors that has been calculated (not measured) to be about 2000x less than typical solder ball-based CSPs used for DRAMs. Lead-free assembly, for either environmental reasons or reduction of alpha particles (the primary source for soft errors in DRAMs), can be achieved using either conductive epoxies or SSD.

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Figure 7. (left) Probe head for contacting multiple —16 in this case — devices at the wafer level, and for testing at speed on the wafer.

In the case of SSD, the contacts on the die are held under compression against gold pads on the module with the use of a lid or a heat sink. The benefits of SSD are that it simplifies rework
epair and eliminates the use of lead in the module.

Electrical characteristics
The MicroSpring CSP has several inherent electrical advantages. Low inductance and low stray capacitance enable high-performance electrical interfaces. Precise control of the electrical parameters through photolithography of the reroute and a tightly controlled spring shape allow precise control of the timing skew and impedance, which improves margins and high-performance yields without compensating for package shortcomings in the silicon or PCB. "Tuning" the interface (Zo, L, R, and C) between the silicon and the system enables multi-gigahertz cutoff frequencies. Pin-to-pin impedance matching of better than ±10% for Zo, L, R, and C is achievable. Since the redistribution traces are small, typically 30-40µm wide for a characteristic impedance of about 50Omega, greater electrical distance — and hence lower cross-talk — between pins is achievable. Further pin isolation and impedance control is achievable if the designer wishes to place ground traces between signals. These traces come at little to no additional cost since the process is lithographic and wafer-based.

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The lithographic reroute metallization can also be tailored for superior power distribution, as shown in Fig. 3. Large metallization structures offer low-inductance, low-impedance, and high-capacitance power structures that reduce ground bounce and Vdd noise at the silicon. Since the technology is a wafer-based process, there is also no inherent penalty for additional power and ground pins. Further, power and ground pins are no longer "package-limited" and can be placed anywhere on the surface of the die.


Figure 9. Close-up of ICs connected with reflowed solder showing a) the air gap and the significant distance from the solder fillet to the die surface; and b) a two-sided assembly with epoxy standoffs.
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For point-to-point interconnect systems, impedance-matched interconnects can be designed. Filter structures that have multi-gigahertz cutoff frequencies can also achieve impedance translations between the silicon drivers
eceivers and PCB traces. In bussed system applications, reduced bus loading is realized through several features of the contact. Since the diameter of the contact is considerably smaller than a solder ball, the PCB pad dimensions, and hence the capacitance, can be made considerably smaller. The impedance of the contact is slightly inductive (<0.8nH) and can be adjusted to conjugate-match the silicon capacitance to a specific impedance value. By contrast, solder balls tend to be slightly capacitive, which increases loading in a bussed architecture.

The contact provides a relatively large vertical standoff distance from the PCB relative to the reroute above the silicon (150-500µm standoff vs. 5µm for the reroute), so that the electrical characteristics of the device are not affected by PCB structures under the die.

Conclusion

Economic scaling in semiconductor backend manufacturing will be enabled by wafer-level packaging and whole-wafer testing of the ICs. A unique approach has been proposed, based on a derivative of a proven semiconductor probe card contact.

For the wafer-level CSP, MicroSpring contacts are being fabricated directly onto silicon wafers for use as the compliant interface to test equipment, and as the soldered or socketed interconnect to circuit boards. At this time, demonstrations have been made of effective whole-wafer contactors and of clamping systems, of test heads for at-speed test at the wafer level, and of test sockets for singulated die. Reliability tests of soldered modules have been performed, showing high reliability for a double-sided CSP module, and good electrical performance has been shown for high-speed ICs. An integrated path to high-volume wafer-level semiconductor backend has been clearly demonstrated.

Acknowledgments
MicroSpring is a trademark of FormFactor Inc. RIMM is a trademark of Rambus.

References

  1. Electronic Industry Report, Prismark Partners LLC, Cold Spring Harbor, NY, 2000.
  2. C. Miller, J. Novitsky, "A Unique Solution to Wafer-Level Processing," Session P-AD1/3-1 to 3-6, Proceedings of the APEX Conference, 2000.
  3. R. Whitten, "Using MicroSpring Contacts for Wafer Level Package and Test," Proceedings of the IEEE Known Good Die Conference, 1999.

John Novitsky earned his BSCS from Michigan State University. He was VP of marketing at MicroModule Systems and worked at Intel on the 386, 486, and Pentium microprocessors. He is a member of IEEE and IMAPS and an editorial board member of Microprocessor Report. Novitsky is VP of business development at FormFactor Inc., 2140 Research Drive, Livermore, CA 94550; ph 925/294-4300, fax 925/294-8147, e-mail [email protected].

Chuck Miller earned his BSEE from the University of Cincinnati. His background is in ASIC and communication systems design, and he has received more than 10 patents in the area of precision timing and test technology. He is the director of electrical engineering at FormFactor and an IEEE member.