Technology News
01/01/2001
US Air Force lab develops defect analysis for GaAs wafers
The US Air Force Research Laboratory (AFRL), Wright Patterson AFB, OH, has developed an automated method for calculating defect density on GaAs wafers. As a result, researchers there substantially increased their understanding of how substrate properties vary and correlate with electrical measurements on devices fabricated on these materials.
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A histogram reveals the distribution of dislocation density measured on a 6-in. GaAs wafer, with the wafer map showing the corresponding spatial variation in the dislocation density. The data is gathered by measuring the infrared transmission at specific wavelengths from a collimated beam passing through the wafer. (Source: US Air Force Research Laboratory, Wright Patterson AFB)
The performance of GaAs devices depends significantly on traps and defects in the crystalline material. A graphics script developed by the AFRL provides quick classification of GaAs wafers based on these traps and defects.
One of the important defects affecting GaAs performance is the EL2 trap — an electronic defect in the crystal whose atomic structure is not fully understood — according to Millard Mier, a research physicist at the AFRL. It is, however, instrumental in producing semi-insulating GaAs crystals by pinning the Fermi level near midgap. Uneven distributions of EL2 can cause problems in GaAs by affecting resistivity and device isolation.
Crystalline dislocations are another important set of GaAs defects. The effects of dislocations on electronic devices fabricated on active layers grown on semi-insulating GaAs is unclear, but dislocations are unlikely to improve device characteristics. Dislocations in GaAs:Si are known to cause dark line defects in lasers and solar cells, leading to premature failure.
The Air Force Research Lab has devised a method of accurately measuring the infrared transmission and therefore the absorption (or scattering) at all locations across a GaAs wafer. From this, defect density can be calculated. The wafer is mechanically scanned past a beam from a tungsten-halogen light source. The collimated light is focused through a monochromator that passes light of a specific wavelength, chosen to match the defect being measured. Neutral EL2 traps absorb 1.1—m wavelength light, while 1.2—m is used to measure total EL2 trap density. Dislocation density is measured at a wavelength where the EL2 trap does not absorb, such as the 1.45—m wavelength used in the figure. Measurement at other wavelengths is required for other sample wafer compositions. For example, total iron density in InP wafers requires measurement at 1.0—m.
The light passes through an electromechanical chopper and is focused into a 0.5mm square spot on the wafer. A Ge diode detector operating in the low-noise zero-bias mode detects the infrared light passing through the sample. A commercial lock-in amplifier detects the light, digitizes its intensity, and the acquisition computer program stores the intensity in a file along with on-wafer coordinates. Measurement of the 16,597 locations required to map a three-inch wafer takes about an hour.
Interpreting such a large set of data can be very difficult. An analysis routine based on software from OriginLab, Northampton, MA, constructs a color histogram by ranking the data into 14 bins and assigning a color to each bin, and then plotting a square of that color at each location where the measured value corresponds to a bin range. This plot provides an easily interpreted map of the measured values keyed to the color histogram (see figure), which furnishes a method of investigating relatively obscure correlations between materials properties and device properties.
The plot of the dataset can be compared to the properties of semiconductor device test structures fabricated on the wafers. Such measurements as Hall-effect for free carrier density and mobility, source-drain resistance, source-drain saturation current, pinchoff voltage, and microwave characteristics such as cutoff frequency can also be plotted as wafermaps. Visual inspection of the plots quickly reveals any rough correlations, and more detailed mathematical correlations can be carried out as desired. — J.D.
Curious-looking device bends light with little loss
At Sandia National Laboratories, a tiny bar that looks like a piece of cheesecloth is bending infrared beams with very little loss of light (see photo). The working part of the bar is fabricated from GaAs. The effect opens the possibility that the simple, inexpensive, essentially two-dimensional technique can drastically reduce the energy needed to start and operate a laser; most energy input for lasers merely compensates for the large amount of light ordinarily dispersed uselessly in the lasing process. This structure might also have application in optical communications and computers.
 Sandia's perforated structure has proven unusually successful in bending infrared light with little loss. Light moves in the x direction. (Source: Sandia Labs) |
The structure illustrated is much like a "wire for light" where hole size and periodicity blocks most light waves while transmitting those in a selected band of wavelengths. Because little light is lost in the selected band, the technique could be used, for example, to relay as well as change the direction of optical signals coming through telecommunications lines. The structure consists of 200nm dia. holes on 416nm center spacing fabricated with electron-beam lithography. Scientists at MIT calculated the needed dimensions of the structure.
Shawn Lin, lead researcher at Sandia Labs, describes the bar as a two-dimensional photonic crystal. "The placement of holes substitutes in the photonic crystal for the spaces between molecules in real crystals. However, while natural crystals are restricted by their prearranged molecular spacing to permit only certain wavelengths of light to pass through them, researchers can vary the spacing of artificial crystal components, thus allowing any selected frequencies within tool limits to pass," says Lin.
The Sandia 2-D crystals have little measurable intrinsic loss or distortion as they guide infrared light around sharp corners. While the Sandia researchers had earlier created similar three-dimensional silicon photonic crystals, the 2-D crystals are cheaper and far easier to build.
Lin says, "Many people have realized the value of such a structure. The problem has been how do you build it?" The problem was that it was thought light would easily escape out the top and bottom of a 2-D structure. Sandia researchers got around that problem by capping the structure with silicon oxide on top and aluminum oxide on bottom. The cladding provides a large difference in the index of refraction and dramatically improves the ability of researchers to keep light traveling within the central portion of GaAs. The cladding process was pioneered at Sandia Labs as part of its groundbreaking vertical cavity stimulated emission laser (VCSEL) research work.
"You might wonder how the cladding keeps the light stable as it passes through holes, since the refractive index of air is lower than the refractive index of semiconductors," Lin says. "This problem vanishes because the distance across the hole is so small that quantum interference effects come into play, and the light merely moves to the next confined substructure."
With the crystal itself fabricated in GaAs, "it is easy to make," says Lin. "The laser and guiding element can be in the same chip: signal binding and switching, all in one place. The hard part is to build the structure without it cracking, and then testing it." — P.B.
Deconvolution technique for CVD and CMP process control
A novel method of "inter-process control" — using metrology data from one process to control another one — can improve run-to-run (R2R) control of the CVD/CMP process sequence. In a presentation at International SEMATECH's Advanced Equipment Control/Advanced Process Control Symposium in September, Jiyoun Kim of the University of Michigan described a technique for extracting post-CVD data that can serve as feedback to the CVD process, as well as feedforward information for adjusting the CMP process to follow. Post-CMP data is then used as feedback for the CMP process.
 Deconvolution of radial and gradient nonuniformity components of deposition thickness data. (Source: University of Michigan IMPACT Group) |
Standard process control of, for example, the thickness of a deposited layer will reflect the range, standard deviation, and other such parameters, but these do not provide information that is directly useful for adjusting a process recipe. The methods advanced by Kim and her co-workers (Chadi El Chemali and James Moyne) extract radial and gradient nonuniformity components from the data (see figure), and these are much more likely to reveal something about the process that can be addressed.
The post-CVD data typically reveals both types of nonuniformity, which are natural outcomes of the process. The placement of wafers in a chamber and the characteristics of process gas flow in the CVD chamber, for example, will create radial and gradient variations in the thickness of deposited layers. The radial component is calculated by taking the average value as a function of radius, and a typical result is shown as R(r) in the figure. The gradient nonuniformity can also be calculated, and this is shown as G(r) in the figure. These results can be fed back to the CVD process to adjust the process to minimize nonuniformities.
Similarly, the information is fed forward to the CMP process for any adjustments that might be required to process that particular wafer. For example, the removal rate could be adjusted as a function of radius to address the radial nonuniformity coming out of the deposition process. The post-CMP data can be used in a feedback loop to adjust the CMP process, if the outcome differs from the target.
Subtraction of the radial and gradient nonuniformities also leaves a residual function (n'(r,q) in the figure), which might reveal some feature of the process that would be otherwise hidden if it were merged in with the nonuniformities.
Kim reported an interesting effect in an experiment that found the radial nonuniformity before CMP increased throughout the wafer runs. This gradual drift could be compensated with process recipes that vary by wafer run. — J.D.
Y-junction carbon nanotubes behave like electronic devices at room temperature
A professor at Brown University, Providence, RI, believes y-junction carbon nanotubes may play a future role as a viable alternative beyond the limits of today's silicon technology.
Jimmy Xu with Brown University's division of engineering, explains, "Today's p-n junction in diodes, heterojunction in transistors, and MOS junctions possess nonlinear current-voltage characteristics that enable signal processing. A goal in nanoelectronics is to achieve similar functionality at the nanometer scale." Xu's work is focusing on carbon nanotubes (CNTs) for molecular-scale devices (see illustration).
CNT structures can be synthesized by arc discharge, laser vaporization, and chemical vapor deposition (CVD). Single-electron devices and field-effect transistors have been shown by placing straight CNTs across patterned gate electrodes. A different approach to forming nanotube devices involves connecting tubes of different sizes to form nanoscale junctions that possess intrinsic device functionality; this approach requires controlled production of such synthetic CNT junctions. Xu tells Solid State Technology, "A template-based CVD technique has recently been developed that allows the reproducible and high-yield fabrication of y-junction CNTs."
As reported recently in the October 16, 2000, Physical Review Letters, Xu and his team of engineers at Brown reported significant conductance measurements on Y-junction CNTs that show intrinsic nonlinear and asymmetric current-voltage behavior at room temperature.
"We performed electronic transport measurements on y-junction CNTs — novel junctions where a large diameter tube branches into two smaller ones — measuring both arrays and individual junctions," Xu says. "Independent measurements using reliable good quality contacts on both individual y-junction and many in parallel show intrinsic nonlinear transport and reproducible rectifying behavior at room temperature. The results were modeled using classic interface physics for a junction with an abrupt change in band gap due to the change in tube diameter."
The y-junction CNTs were produced by CVD growth in branched nanochannel alumina templates. This method produces multiwalled CNTs in aligned arrays (a typical array density is 1010/cm2) with adjustable stem and branch tube diameters. The y-junctions are typically 6-10—m long with stem to branch diameter ratios of 50:35nm and 60:40nm.
For electronic transport measurements on individual y-junctions, Xu's team chemically removed them from their growth template and put them onto patterned electrodes. "To make low resistance contacts to the y-junction, we first sputtered an island-like film of gold or silver onto the sample. Next, we applied a large bias — typically 10-20V — between the two electrodes containing the y-junction while limiting current. Initially, we did not observe a current flow; however, over a period of 1-3 hrs, the current increased and eventually saturated to a fixed value," says Xu. Subsequent examination of tube ends revealed a migration of the metal particles, presumably induced by the high electric field at tube tips. "We found this method produced reliable and reproducible contacts to individual y-junction nanotubes. The current-voltage data displayed distinct and reproducible asymmetric and rectifying behavior with current flowing more easily under negative bias. This is an exciting demonstration of nanotube electronics, made possible by a team of creative researchers, including Chris Papadopoulos, Alex Vedeneev, Andrei Rakitine and Jing Li, and by support from the Office of Naval Research and the Air Force Office of Scientific Research," he said. — P.B.
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Sarnoff's simplified ESD protection for silicided devices
A novel design and layout strategy developed by Sarnoff Corp., Princeton, NJ, simplifies the wafer process steps required to create I/O cells that are safe from electrostatic discharge (ESD) damage. The new approach, dubbed TakeCharge, eliminates the need for "silicide blocking," in which extra process steps are used to keep silicide out of shallow junctions in devices between the circuit core and its I/O pads. Junction silicidation reduces series resistance, which increases device speeds, but the lower resistance makes the devices in some locations more susceptible to ESD events. The reliability is unacceptable, so silicide blocking is used for those endangered junctions.
Sarnoff's technology eliminates the need for silicide blocking by increasing the series resistance in the interconnect, with extra via chains through multiple metal layers and contacts. A polysilicon resistor (plus two contacts) can also be included to increase the ballast resistance, as shown in the cross-section of the structure in the figure. The silicide can remain in the junctions of the at-risk locations, allowing the increased device speeds and lower power, while the extra resistance in the interconnect spreads the energy of an ESD event. With back-end ballast parallel resistors, there is a negative feedback effect as well, in which a voltage that builds up at one resistor (when current begins to focus in an area) forces the current to become more evenly distributed throughout the device.
The layout contributes to the reliability with segmented metal "fingers," as shown in the layout view of the figure. Multiple narrow fingers, each feeding into a single contact to the active device, can be used in the ESD sensitive areas to provide a proper resistance, rather than using wider sheets of interconnect metal to contact silicide-blocked active areas. This layout does not increase the device area beyond that required for devices with silicide blocking.
The TakeCharge technology has patents pending and is available for licensing, according to Sarnoff. It has been implemented in different CMOS technologies down to the 0.18—m process node. — J.D.
Schlumberger makes progress in flip chip probing
First silicon de-bug can be difficult with flip chip ICs, but silicon designers now have a better tool for this with the IDS2500 laser probe system recently announced by Schlumberger Semiconductor Solutions, San Jose, CA.
The system takes advantage of the electroabsorption phenomenon, in which the reflectance characteristics of a device change when a transistor switches. A near-infrared (NIR) laser is sent through the flip chip IC from the back, with the 1054nm laser wavelength being chosen because it transmits through silicon. A reference beam and a probe beam are used, and the phase interference between the reference and reflected probe beam identifies when a transistor is switching.
 Schlumberger's IDS2500 laser probe system |
This phase interferometer detector (PID) technology is a significant improvement over the previous technology, with much greater sensitivity and about a four-fold increase in throughput, according to Xavier Larduinat, marketing director for probe systems at Schlumberger. A previous generation of the equipment measured amplitude modulation instead of the phase interference, and since the amplitude variation was at the ppm level, a complex set of electronics was needed to measure and amplify that signal.
The IDS2500 can probe through 150—m of silicon and has been verified on 0.18—m design rules. Larduinat noted that because of the many metal layers on top of ICs these days, backside probing with this technique should find growing applications. It is currently used primarily for de-bug of flip chip microprocessors; the technology was co-developed with Intel when it began focusing on flip chip technology.
Another flip chip probing technology, IBM's picosecond imaging circuit analyzer (PICA), was licensed by Schlumberger last year. According to Larduinat, though, the PICA technology is more appropriate for failure analysis. It relies on imaging of photons emitted when a transistor is switching, so it can be used to watch the operation of a device. This is useful for failure analysis. On the other hand, the IDS2500 is probe-based, so it would not be appropriate for failure analysis unless you already know where the fault is. The IDS2500 is faster than PICA, so it is more efficient for design verification and de-bug of timing issues.