New scanning technique: Will it make coating the low-cost alternative for low-k films?*
01/01/2001
Tokyo Electron Ltd. and Toshiba Corp. plan to introduce new scan-coating equipment this year that could significantly reduce the cost of making low-k dielectric films, and, eventually, of applying resists as well. The new approach reduces material use compared to spin coating, while apparently avoiding the high capital costs of CVD.
In conventional spin coating, the centrifugal force that spreads the coating material evenly over the surface spins most of the material right off the wafer so it's wasted. This new nozzle-scanning process sprays a fine coating directly onto the wafer from a moving nozzle scanning back and forth across its surface. TEL and Toshiba say they've managed to control the spray to apply a usable thin and even coating, while moving the sprayer fast enough to maintain throughput thanks to a new spray pump and a better nozzle drive mechanism.
 An illustration showing how the new scanning technique works. |
Using the new technology, the companies say they can make a 1—m-thick coating of low-k dielectric film on an 8-in. wafer that varies by only ±3% (average thickness is 991nm, 3s = 261nm). Throughput is around 1 wafer/min, about the same as for spin coating. And the process uses only 10% as much material as spin coating to coat the wafer.
TEL and Toshiba control the amount of spray by controlling the pressure in the piston of the spray pump, and by reducing the diameter of the opening in the nozzle to 10-100—m. This reduces the volume of spray, down to about 1cm3/min compared to 1cm3/sec in conventional spin coating.
Improvements to the nozzle's drive mechanism increase its speed to several meters per second to maintain throughput. When the nozzle swings off the edge of the wafer and reverses direction for the return trip, acceleration from full stop to full scanning speed is 98m/sec2.
While the current ±3% precision of the coated surface is sufficient for low-k dielectric films, researchers will have to get it down to ±1% to be able to use this scanning equipment for photoresist application. They're looking at new resist solvents for better control of spray volume and better coating characteristics.
Both companies plan to commercialize scan-coating products by the second half of this year. — Keiji Sowa
Three new Japanese research projects slated to begin this year
Over the last year or so, the idea of government, industry, and academia working together to create a "post-Silicon Valley" era has been percolating through Japan. While all parties agree that the development of semiconductor technology is key, there isn't a consensus on priorities. Corporate and university sectors are more explicitly interested in restoring Japan's competitive position in the semiconductor industry.
 Making sense of the tangled web of relationships between players in Japan's new chip research consortia. |
"We're in pursuit of the way for Japan to win," says Tohoku University professor Tadahiro Ohmi, who will lead one project. Government officials prefer to stress how advances in semiconductor technology will spur the development of the electronics industry as a whole. "We want to link semiconductor breakthroughs to the development of the information technology industry," says Akira Kubota, director of the Ministry of International Trade and Industry's Industrial Electronics Division.
The first of two government-sponsored projects, The Next-generation Semicon-ductor Research and Development Project, will focus on developing 0.07-0.05—m process technology. It will occupy about a third of a new 4500m2 government cleanroom to be built in Tsukuba. Though some $150 million (¥108/$1) was first budgeted for this lab in fiscal 1999, it isn't expected to be ready for operation until 2002. MITI is requesting another $40 million for the project this year.
Project leader Masataka Hirose, professor at Hiroshima University, aims to build up a world-class research center over the next three years. Research themes under consideration are 1) high-k dielectric gate insulating film; 2) low-k dielectric interlayer insulating film; 3) mask technology; 4) new process technology; and 5) system architecture.
The second government project, Development of Basic Technology for Process Equipment for Advanced Devices, aims at developing next-generation equipment and production lines. About half the initial $14 million budget will go toward work on small-scale production, a minifab line running 2000- 3000 wafers/month, under the direction of Tohoku University's Prof. Ohmi.
"A minifab is useful for making LSIs for digital consumer electronics gear where users want fast ramp up, and demand changes rapidly," Ohmi said. He wants industry cooperation to build a cleanroom at Tohoku University for this minifab. He foresees investing some $90 million in the first 3 years to build a line running 2500 wafers/month, using compact equipment, each unit handling several different processes. Then he hopes to invest another $45 million or so to shrink the equipment down even further.
Industry also has a new semiconductor research consortium of its own under the auspices of the Electronics Industry Association of Japan, focusing on developing 0.1-0.07—m process technology. All 11 of the big names in Japanese semiconductors plan to participate in this project, dubbed Asuka, to the tune of a whopping $700 million budget, spread over five years. The project will occupy the other two thirds of the new government-funded cleanroom in Tsukuba.
A working group focusing on process technology will center around Selete, the existing 300mm equipment consortium. Another working group will focus on chip design, centering around STARC, the Semiconductor Technology Research Center. MITI officials, however, complain that industry has no clear scenario for the design project. — Hiroshi Asakura
*These stories were translated for SST from the October 2000 issue of Nikkei Microdevices, our partner in Japan.