Transistor performance: the impact of implant doping accuracy
01/01/2001
Babak Adibi, Applied Materials Inc., Santa Clara, California
Viktor Meniailenkov, Integrated Systems Engineering, San Jose, California
overview
Transistor fabrication requirements are emerging as the next critical set of challenges to continue ITRS-driven progress. Doping accuracy for parametric and conductive implant applications is especially important for sub-0.13—m-generation devices. As shown here, TCAD simulations can be used to understand how equipment factors, such as implant angle accuracy, affect device performance.
One conclusion that is evident from the ITRS1999 roadmap [1] is that improvement in transistor performance is a critical challenge for the semiconductor industry, beginning at the 130nm technology node. The transistor itself constitutes less than 5% of the thickness of the device, but it has more than half of the critical identified issues. In particular, it is generally accepted that implant equipment suppliers need to focus on much better accuracy of dopant, as shown in Table 34a of ITRS1999, where the variation of dopant depth and dose is discussed for the first time.
Of the two main implant application areas — "conductive" and "parametric" (see Fig. 1) — the biggest challenges reside with the parametric implants, where small variations in dopant placement (e.g., halo implant) can have magnified effects on the transistor's performance. In this article, TCAD simulation [2] and experimental results are used to identify several potential areas where improvement is needed and to show specific ways in which implant equipment suppliers can address these emerging requirements.
Device fabrication doping challenges
According to the ITRS roadmap, transistor channel engineering is confronted with two major challenges. The first is in the critical requirements involved in maximizing the drive saturation current (Idsat) and minimizing the short channel effect [3]. Accurate control of implanted profile and the diffusion of such dopants addresses this requirement. The main processing steps that affect these profiles are the implants that change the conductivity of the substrate and the subsequent thermal annealing step that completes fabrication of the basic transistor. These implantation steps include source and drain (S/D), source/drain extension (SDE), and polysilicon doping, which are called "conductive" implants. For sub-0.13—m technology nodes, they should minimize the junction lateral abruptness (<5nm/decade), junction depth (<300Å), and resistivity by exceeding dopant activation of >1 x 1020/cm3 in the channel region. In general, today's most advanced low-energy implant and RTP technologies are meeting these requirements. For sub-100nm technology nodes, the advent of low-energy implantation and laser annealing can meet the ITRS requirements. Much work is being carried out to meet this challenge.
The second implant challenge, after the formation of the basic transistor by conductive implants, is to optimize device parameters. Some of the requirements for shrinking device technology are to control the threshold voltage (Vt) better and to minimize leakage currents within the transistor. Accuracy of dopant placement in the transistor becomes increasingly critical to meet these goals. These "parametric" implantation steps include threshold voltage adjust, halo, super halo, anti-punchthrough, pocket, and various retrograde well implants. For such exacting parametric implants, chipmakers are seeing the need for much tighter control and calibration of the species, incident angle (to <1°), energy (to <1%), and dose (to <0.5%). Many of these requirements are not being met by the parametric implanters now on the market (such as medium-current and high-energy implant tools), and new equipment designs are needed to overcome the challenges. This is the next battleground for implant for device performance improvement in the next few years.
Using a 0.15—m, high-volume logic fab as an example, it is reported that for a halo implant, a 1° error in implant angle can shift Vt by as much as 7-10mV. This is more than 5% of the Vt shift budgeted for the whole fab line [4]. Such inaccuracies are commonplace in today's single-wafer, medium-current systems, where implant angle variation can be as much as ±2°.
It is also reported that, for a high-energy implant performed using a batch high-energy system, a variation in incident (cone) angle of as much as ±1.2° across the wafer can cause significant variation in punchthrough voltage (30%) and leakage current (1-2 decades) [5]. To minimize such angle variation, it is critical to eliminate the cone angle by converting to serial (single-wafer) high-energy systems.
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Furthermore, for the high-energy well implants that are carried out at normal incident angle to avoid shadowing, control of channeling is critical. For example, at energies >100keV, the critical channeling angle beyond which ions de-channel is <1.5° for <100> silicon. A slight deviation in the implanted incident angle can therefore cause de-channeling, affecting the atomic profile in silicon. Older implantation systems (both medium-current and high-energy) that cannot control implant angles to better than the critical channeling angle have demonstrated "twin peaked" atomic profiles. Such poorly defined atomic profiles can reduce the device immunity to latch-up. (It should be noted that there have been no reports showing a detrimental effect of cone angle using higher-dose, conductive source/drain batch implanters for technologies down to <0.1—m. These batch systems continue to benefit from higher beam current transmission over the shorter beam line.)
Using TCAD to relate equipment to device parameters
Ion implant equipment manufacturers have generally relied on their interpretation of device specifications or roadmaps to guide them in tool development. These specifications are supplied by device design engineers who invariably use sophisticated TCAD software, and they are in the form of junction leakage, voltage threshold, Idsat etc. Translation of such parameters into process equipment capability can be subjective and may not lead to the most suitable tool.
Today's state-of-the art TCAD simulation tools [2] allow equipment development engineers to establish a very accurate relationship between device parameters and process equipment parameters. Full calibration of this software is required to allow equipment suppliers to study the impact of the precision, accuracy, and variation of their equipment parameters on device performance.
Effects of doping accuracy on parametric implants
A TCAD package from ISE Inc. was used to study the effect of doping accuracy for a halo implant in a 0.18—m logic device (BF2, 60keV, 1 x 1013/cm2, quad implant, and annealed). It is shown that an implant angle variation of ±2° can cause variation in the net doping isoline. Figure 2 shows a cross-section of a critical portion of the channel region, and it shows only the critical dopant concentration isoline between 5 x 1017/cm3 and 1 x 1018/cm3, which has the greatest influence over device function. There were no variations in the isolines above 1 x 1018/cm3 as a result of the inaccuracies in the implant angle. The isoline position directly reflects the electrical characteristic of the device.
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Figure 2. Using TCAD software, the variations in net doping isolines are shown for a 180nm technology transistor channel cross-section for a variation in halo implant incident angle (BF2, 60keV, 1 x 1013/cm2, 35°, quad rotation +, annealed).
Further use of the TCAD package to study the device characteristics shows that small angle changes for a halo implant can cause up to 60% change in leakage current and 5% shift in threshold voltage (Table 1). Other device parameters, such as drain induced barrier lowering (DIBL) and body effect, are not affected adversely by such angle inaccuracy.
The leakage current is particularly impacted, since it is directly affected by the surface doping concentration variation in the sides of the doped channel region, near the Si/SiO2 interface. This can change the channel length and thus alter the leakage current. A slight deviation in halo implant incidence angle can introduce large variation in the dopant distribution in that region, as shown in Fig. 2.
The threshold voltage is less sensitive than drain saturation current to the variation in the halo implant incident angle. The Vt is primarily determined by the doping in the main body of the channel. The change in incident angle does not strongly affect the doping in the channel itself but only on the sides of the channel. The Vt shift is proportional only to the square root of this doping concentration.
DIBL is the measure of the change in the potential energy barrier in the middle of the channel, between the source and the drain region, at the silicon interface. Such a barrier is caused by the junction depletion region charges (which in turn arise from the built-in p-n junction, the electric field, and the reverse bias drain voltage), as well as the gate charge. This barrier is particularly affected by the channel length and the main channel doping. The variation in halo implant incident angle, therefore, does not affect this parameter. The body effect or substrate sensitivity is directly dependent on substrate dopant concentration, which is not directly affected by the halo implant.
Angular variation can result from excessive tolerance build-up in poorly designed implant tools, offering different incident angle depending on the position of the E-chuck prior to implant. It can also be more symptomatic and can happen after E-chuck maintenance, for example, where poor re-assembly can cause angle deviation if not checked and re-calibrated.
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The substantial impact of angle variation requires an ability to calibrate and correct this critical equipment parameter before each implant step or wafer lot. Such capability ensures implant parameter repeatability, which is important for implant-to-implant, system-to-system, and fab-to-fab repeatability. The above discussion equally relates to both implant tilt and wafer twist angle control, although the impact of wafer twist is an order of magnitude lower than tilt angle, as measured by sheet resistivity.
The requirement for doping accuracy becomes much more pronounced as geometries shrink. Further simulation work (Table 2) was carried out to investigate the impact of angle inaccuracy on devices with geometries from 0.35-0.13—m. Over this range, an angle variation of ±2° can cause a twofold shift in voltage threshold and a threefold increase in leakage current.
Table 2 clearly shows that the effect of implant angle variation is particularly pronounced at 130nm technology node simulations. One of the reasons for this study is to show that although present-day implant systems may be adequate in meeting >180nm technology requirements, they may not meet the stringent requirements for smaller geometry devices.
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Using TCAD, one could conclude that new implant tools with unprecedented control over doping accuracy are required. In case of angle accuracy, the device requirements dictate control and calibration to <±0.5°, in line with wafer slicing angle. The next challenge will be to improve the wafer slicing angle control. Other TCAD simulation shows that the impact of dose and energy variation for a halo implant can be as critical as angle variation.
Experimental verification of TCAD results
To verify further the impact of angle accuracy from the above simulations, a series of experiments studied the effect on sheet resistivity (Rs), therma-wave (TW), and junction depth, as measured by spreading resistance probe (SRP) measurements. Figure 3 shows that an angle change of ±2° for a halo implant can lead to about 8% change in Rs. It can also cause some minor change in the TW number (not shown in the figure). This is due to the impact on channeling, which leads to variation in junction depth. Using SRP measurement, the TCAD simulated variation in junction depth of about 10% is confirmed, indicating that a ±2° implant angle change can adversely affect device performance.
Next, a series of experiments was performed to study the impact of implant parameter variation across a wafer at higher energies. For example, a phosphorus 200keV 1 x 1014/cm2 implant at 0° tilt and 0° twist was performed on a 300mm wafer. These conditions were selected in order to use axial channeling as a way to investigate the impact of angle variation across the wafer.
 Figure 3. The impact of tilt angle variation on sheet resistivity, SRP Rs, and junction depth for a halo implant. |
The atomic profile was measured — using secondary ion mass spectroscopy (SIMS) — numerous times on the center of the wafer and at four sites within 5mm of the edge of the wafer to study the impact of implant parameter variation on dose, projected length (Rp), peak concentration (Cp), and junction depth (Xj). At this condition, the channeling critical angle is <1° for <100> silicon, making the control of incident angle much more critical. The data (not shown here) show that the SIMS profiles were fully superimposed, with no visible variation across the wafer, indicating that implant parameters were identical at all points. In addition, no artifact near the surface of the wafer was noted, indicating no Aston band and charge exchange contamination. Further and detailed analysis of such atomic profiles revealed no deviation in the atomic profile.
Effect of doping accuracy on a conductive implant
The authors also investigated the impact of equipment parameter variation on conductive implants used for channel engineering. The effects on the formation of ultrashallow junctions and thus device performance that were studied include implantation energy, angle, and dose, as well as RTP anneal temperature, uniformity, ramp rates, and cool-down rate. It was concluded that if the energy of a low-energy implant such as SDE at 200eV is not controlled, the junctions formed can be affected adversely. Traditionally, a power supply that generates the required voltage has to provide voltages for a wide operating range (i.e., 200V to >80kV). The accuracy and calibration of voltage over such a wide operating range is critical. For example, traditional power supplies have an accuracy of 200V for >100kV supply. This 100% error is excessive for a 200eV SDE implant. Such inaccuracies will not meet the device requirements for <0.13—m technology [6].
Conclusion
The latest ITRS roadmap clearly shows that stringent requirements for transistor fabrication will drive both device and equipment development in the next few years. Although the role of ion implantation is a critical element in transistor formation, the design of current implant tools is, in most cases, insufficient to address the doping accuracy requirements of parametric (e.g., halo and well) implants as well as conductive (e.g., SDE) implants for sub-0.13—m-generation devices. In particular, the limitation of implant angle accuracy in the parametric (medium-current and high-energy) applications is one of the key challenges to making improved transistors. TCAD simulation has highlighted several areas where improvements in equipment design can help equipment manufacturers meet users' most advanced implant requirements.
Acknowledgments
The authors would like to thank many people at Applied Materials for their contributions: in particular, Majeed Foad, who carried out the parametric implant experimental work; Amir Al-Bayati, who carried out the conductive implant experimental work and assisted with the device implications; and Causon Jen for much of the field data. Much thanks is also due to many people at Integrated Systems Engineering (ISE) for carrying out the TCAD simulation. Rimydas Mickevicius and Simeon Simeonov of ISE provided the inputs for understanding the device implications further.
References
- ITRS1999 at http://public.itrs.net/files/1999_SIA_Roadmap/FEP.pdf.
- TCAD paper to be published by ISE at the December 2000 International Electron Devices Meeting.
- Scott Thompson, Paul Packan, Mark T. Bohr, "MOS Scaling: Transistor Challenges for the 21st Century," Intel Corporation at: http://developer.intel.com/technology/itj/q31998/articles/art_3.htm
- Private communication.
- D. Kapila, et al., IEEE Trans. Semicon. Manufac., Vol. 12, pp. 457-461, 1999.
- Amir Al-Bayati, et al., "Spike Anneals for Ultra-low Energy," European Semiconductor, p. 41, July 2000.
Babak Adibi holds a PhD and MSc in ion implantation and nuclear physics from the University of Surrey, England, and a BSc from the Imperial College of Science and Technology in London, England. He is the head of group marketing for the parametric and conductive implantation products business group of Applied Materials. Since joining Applied Materials in 1985, he has held several positions in process engineering, technology, product and program management, and strategic marketing. Applied Materials, 3050 Bowers Avenue, M/S 0134, Santa Clara, CA 95054; ph 408/235-6262, fax 408/986-2833, email [email protected].
Viktor Meniailenkov received his MS in electrical engineering in 1979 and his PhD in the physics of semiconductors in 1986, both from the Moscow Institute of Electronics Engineering, Zelenograd, Moscow, Russia. From 1986 to 1996, he worked for the Research Institute of Molecular Electronics, Zelenograd, where he specialized in development and application of VLSI process simulation software. He joined Integrated Systems Engineering (ISE), Zurich, Switzerland, in 1997. Since 1998, he has worked in the San Jose office of ISE as a senior application engineer specializing in advanced process simulations.