Process technology update: Progress on all fronts
01/01/2001
Special Report
ULTRA-SHALLOW JUNCTIONS
Controlling the input, measuring the output for USJs
The creation of ultra-shallow junctions (USJs) has driven significant recent developments in ion implantation, thermal processing, and metrology. Lenny Rubin, principal scientist at Axcelis Technologies, reports that the challenges for the near future are now less scientific and more in the area of equipment engineering: "It is now clear that conventional mass-analyzed ion implantation and RTP annealing will be adequate for producing both n- and p-type source/drain extension regions that simultaneously meet the ITRS requirements for sheet resistivity, junction depth, and lateral abruptness for at least the 100nm device node. With much of the relevant scientific phenomena well understood, the challenge of coming years will be to produce the hardware that performs best in volume manufacturing." Babak Adibi, Applied Materials, also sees many of the challenges in terms of equipment performance. (See below.)
Process trends ending
Recent work by Aditya Agarwal of Axcelis demonstrates that some of the directions in shallow junction formation have reached their limits [1]. For example, increasing the dose while decreasing the beam energy has helped the formation of shallow junctions, but Agarwal showed that dopant self-sputtering — the removal of dopant atoms from near the surface layer during ion bombardment — increases with increasing dose, and that the effect is more severe for sub-500eV beams. This makes it undesirable to decrease the energy below some level (about 500eV for boron), or to increase the as-implanted dose above a certain level.
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A p+/p doping profile, resulting electric field (E), and excess carrier distribution under 10mW illumination into a 2—m dia. spot. Courtesy of Boxer Cross
Similarly, a fast ramp rate in the thermal annealing process has been a desired process feature, but ramp rates beyond about 100°C/sec do not reduce junction depth any further, according to Rubin. In fact, a higher ramp rate can merely delay effects such as transient enhanced diffusion until the ramp-down portion of the anneal. Given the difficulty of controlling ramp rates, it is no longer a good strategy to increase ramp rate beyond that level. Instead, other process parameters can be manipulated to get the same result.
USJ metrology
Improved dopant profile metrology is often cited as a critical need for continuing the progress in shallow junction formation [2, 3]. A promising technique that nondestructively measures implant depth (Xj), energy, and dose on product wafers is carrier illumination (CI), an optical method developed by Boxer Cross Inc.
 Shown in this collage are images from Axeclis' low-energy and RTP systems. |
Junction depth is typically measured by spreading resistance probe or secondary ion mass spectroscopy, both of which require special sample preparation. This is becoming unacceptable, though, according to Peter Borden, CTO at Boxer Cross. "The measurement of implant abruptness in production is seen as rapidly becoming a requirement," according to Borden. (See "Critical doping trends driving advanced USJ metrology.")
The CI technique uses a laser with photon energy above silicon's bandgap to generate excess carriers. The excess carrier concentration changes significantly at the edge of a doped region (see figure), creating a gradient in the index of refraction at that depth. Light from another laser is reflected from this region of varying index of refraction, and analysis of that reflection allows the depth profile to be determined. The depth resolution is excellent because silicon's high index of refraction makes the measurement wavelength only 270nm. With a full 2pi phase shift seen in 135nm, and a noise-limited phase resolution more than 0.5°, the depth resolution is better than 2Å [4]. This is a critical capability for approaching junction depths in the ITRS. — J.D.
References
- A. Agarwal, "USJ Formation Using Ion Implant. & RTA," XIII International Conference on Ion Implantation Technology, 2000.
- M.I. Current, "Ion Implantation Technology for Processing of Electronic Materials," AVS 1st International Conference on Microelectronics and Interfaces, 2000.
- S-P. Tay et al., "Manufacturing Control of USJ Formation by RTA," 7th International Conference on Advanced Thermal Processing of Semiconductors, 1999.
- P. Borden, "Junction Depth Measurement Using CI," Int'l Conference on Characterization and Metrology for ULSI Tech., 2000.
Role of doping accuracy for sub-0.13—m technology
One of the major challenges of transistor fabrication at the sub-0.13—m node is accurate placement and activation of dopants in the silicon. Traditional equipment used for all implant steps can no longer meet stringent device requirements. Today, a variation in voltage threshold of <100mV across the wafer is excessive. Most 0.13—m devices can only tolerate <25mV variation. Similarly, dopant placement in the device's source and drain regions, specifically the extension region, requires control of the junction depth (<300Å), junction abruptness (<5-10nm/decade), and dopant activation (>1 x 1021/cm3).
Equipment used for parametric implants (voltage threshold adjust, halo, and well) must provide incredible accuracy for beam incident angle, ion energy, and dose. Device TCAD software is used to establish the relationship between device parameters and equipment parameters. For example, the total tolerable incident angle accuracy (<1°), energy set-up precision (<1%) and dose uniformity and repeatability of <1% are required to meet sub-0.13—m requirements. An angle error of <2° can lead to a >5% change in the threshold voltage.
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With conductive implant steps, implant energy accuracy and thermal processing temperature control are critical. Energies must be controlled to within <10V for a 200eV implant, rather than the traditional ±100V. At the same time, rapid thermal processing temperature control and uniformity of <1-2° across the wafer are required for more repeatable device parameters.
Ultimately, as transistor improvements become an increasingly integral component in perpetuating Moore's Law beyond the 0.13—m node, accuracy of dopant placement for all implant steps will be fundamental.
Babak Adibi, senior director, global product management, Implant Division, Applied Materials
Critical doping trends driving advanced USJ metrology
The ITRS shows the implant drain extension depth (Xj) scaling from 36-60nm today, to 24-40nm in 2004. Obtaining dopant activation while minimizing diffusion is a critical issue. This has driven the development of the low-energy implanter and annealing module, which is increasingly being implemented in production. Spike anneals, with near-zero dwell time at peak temperature, are being used to provide high activation while minimizing unwanted dopant diffusion. In the future, this may not be enough. Laser thermal annealing and selective epitaxy show potential for offering an order of magnitude increase in activation while maintaining shallow junction depths.
Additionally, pre-amorphizing implantation, where silicon or germanium is implanted into the silicon to create an amorphous layer, is being used to create shallower junctions. At these reduced dimensions, "lateral abruptness" (steepness) of implant profiles is increasingly required to minimize voltage drop between the S/D and the channel. Currently, abruptness is being pursued through critical control of the low-energy implant and annealing module. Longer-term solutions may require alternative doping techniques.
Several important trends are developing in channel engineering. The lower operating voltages reduce the margin on the threshold adjust (VT) implant process. Super steep retrograde channel techniques are being used to confine the channel. The Gaussian profile drop between the buried implant peak and the surface sets the channel doping. The consequence is that control of both dose and energy become critical. Dopant species such as indium and antimony are increasingly being used for these implants as they are heavier and diffuse less readily during thermal activation.
Peter Borden, CTO and executive VP, Boxer Cross Inc.
DEPOSITION
Assault on ITRS roadblocks led by atomic layer deposition
Atomic layer deposition (ALD) has been identified as the solution for many of the red boxes found in ITRS99 [1]. The key capabilities of ALD — very thin layers, excellent process control, engineered materials — are critical in many processing areas. Although originally developed for other types of devices, ALD is now a critical process for continued advances in the semiconductor industry. (See "Emergence of atomic layer processes" for more information on this technology.)
High-k gate dielectrics
One application where significant progress with ALD has recently been made is high-k gate dielectrics. Recent work by ASM International has demonstrated ZrO2 as a very promising candidate. Along with process advantages, ZrO2 is an appealing material for high-k gate dielectric because of its high permittivity (k = 22) and thermodynamic stability in contact with silicon up to 900°C [2].
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Figure 1. Atomic layer CVD growth mechanism of the high-k gate dielectric ZrO2 from ZrCl4 and H2O. Courtesy of ASM International
The ALD process for ZrO2 is illustrated in Fig. 1. Generally, ALD requires that the metal compound precursor and nonmetal compound precursor (ZrCl4 and H2O, respectively, in the case of ZrO2) are introduced alternately instead of simultaneously, as in standard CVD processes. This results in the layer-by-layer growth that creates the characteristics of ALD films, making them appropriate for several applications.
An example of the ability to engineer materials for this application is shown in a recent announcement from Philips and ASM. With ALCVD, they produced a gate dielectric stack with an equivalent oxide thickness of 1.1nm, which is not required until the 70nm technology node. The film consists of zirconium, aluminum, and oxygen; a layer that thin with the right combination of materials was possible only with an ALD process.
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Figure 2. AFM images of a) 7nm ALCVD TiN deposited at 400°C, with RMS roughness of 0.75nm, and b) 13nm I-PVD TiN, with RMS roughness of 1.80nm. Courtesy of ASM International
(See "Equipment and process considerations for ALD" for further discussion of equipment trends.)
Barrier films for Cu metallization
IMEC has shown that TiN films created with ALCVD can be barriers for Cu metallization [3]. The density of ALCVD TiN is comparable to bulk values, and the microstructure has a finer grain structure than films deposited with other processes. The conformality of the films is excellent, and the surface roughness compares favorably to that of ionized physical vapor deposition, as shown in Fig. 2. These properties are critical for reliable interconnect structures. IBM has also shown ALD of Ta and Ti as Cu diffusion barriers [4]. — J.D.
References
- "1999 Roadmap: Solutions and Caveats," Solid State Technology, Vol. 43, No. 5, p. 76, May 2000.
- S. Haukka et al., "Atomic Layer Chemical Vapor Deposition of high-k Gate Dielectrics," Semicon Europa, 2000.
- A. Satta et al., "Structural and Chemical Characterization of TiN Thin Films Deposited by ALCVD as Barriers for Cu Metallization," MRS Spring Meeting, 2000.
- A. Sherman et al., "Atomic Layer Deposition (ALD) of Ta and Ti for Interconnect Diffusion Barriers," 2nd International AVS Conference on Advanced Materials and Processes for Microelectronics, 2000.
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Equipment and process considerations for ALD
ALD shows great promise for the manufacture of high-k dielectrics, thin metal electrodes, and barrier or Cu seed layers in sub-0.10—m interconnect devices. The process appears to have several advantages over traditional CVD: it can be done at lower temperatures; uses a wider range of precursors; produces very thin films; and inherently obtains 100% step coverage and excellent conformality, with lower impurity levels. Deposition rates, however, are limited by the ALD growth mechanism. By definition, the thickness of each cycle grown cannot exceed a few angstroms as determined by the lattice constant of the materials. ALD is therefore targeted at very thin films, primarily gate dielectrics, DRAM capacitor dielectrics, and diffusion barriers.
The nature of the ALD process is such that it can be done in a simplified reactor, where gas flow and temperature uniformity will be relatively unimportant. Instead, the hardware design will focus on preventing deposition on the reactor interior and wafer backside. Development efforts are focused on creating chambers with high throughput, long mean wafers between cleans (MWBC), and low defect density. Reliable and precise control of reactants, quick removal of extra reactants and reaction by-products, and short cycle time control will also be critical to the success of this emerging technology.
Ming Xi, director, ALD Product Unit, Applied Materials
Emergence of atomic layer processes
When Tuomo Suntola invented atomic layer epitaxy (ALE) some 20 years ago, critical feature sizes of integrated circuits were still in the micron range. The thinnest layer was still on the order of 100nm. The strength of ALE was the controlled deposition of very thin (<10nm), high-quality layers. (The original process was for ZnS films for electroluminescent devices.) Accordingly, ALE was not immediately seen as a technique to be applied for the semiconductor market.
In 20 years, many things changed. Aggressive scaling of critical feature sizes led to lateral dimensions approaching 100nm, with the thinnest layers approaching atomic dimensions. One good example is the gate dielectric. For 100nm technology, only 1nm, or about four atomic layers in silicon oxide equivalents, are needed. Clearly, the aggressive scaling has now made applications of the Suntola invention appropriate for integrated circuits.
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ASM International has further developed the ALE technique and is now making the technology available to the semiconductor industry as atomic layer CVD or ALCVD. The first applications are, indeed, the thinnest of the layers and those with the highest quality demands. The thickness of these layers can be controlled simply by counting the cycles, and the process will provide perfect uniformity, coverage, and smoothness over even the most challenging topography. Composition can also be modified and controlled at the atomic level, thus providing an opportunity to create new dielectrics and barriers with material properties that cannot be easily obtained by other means, and certainly not at that level of control. Furthermore, continued scaling of critical IC feature sizes will lead to more and more applications coming into the realm of ALCVD.
Acknowledgments
Atomic Layer CVD and ALCVD are trademarks of ASM International.
Ivo Raaijmakers, CTO, ASM International
New capabilities with 3-D laser etching
As the technology for high-volume wafer processing continues to be improved, new developments promise entirely new capability, particularly for true 3-D etching of silicon. Deep reactive ion etching has greatly expanded the practicality of a wide class of MEMS structures, but this technique is still considered "2-D" since it creates deep extrusions of structures defined by intrinsically 2-D lithography. A true 3-D silicon etching process has been developed with laser etching and a chemical (halogen) assist.
 3-D structure created in silicon with laser etching and a halogen assist. Courtesy of Revise Inc. |
In this method, a green-wavelength laser beam is focused to a several-micron spot on the silicon substrate in the presence of a chlorine ambient of several hundred torr. The laser actually melts a tiny volume of silicon, which then instantaneously reacts to stable volatile silicon tetrachloride. The reactive ambient is essential in order to get clean, debris-free surfaces in comparison, for example, to pure laser ablation, which has limited application in silicon. An extremely high etch rate exceeding 100,000—m3/sec is achieved while retaining micron-scale resolution. In the Revise tool, a high-speed scanner moves the microscopic etch spot at rates of 20mm/sec in a 3-D scan pattern. The silicon is etched, plane by plane, using a data file. This stereolithography-like strategy allows a wide class of truly 3-D structures to be realized. (See photo for example.) The extension of laser microchemical etching methods into three dimensions will be particularly important for MEMS. An immediate application has been the local thinning of silicon for "surgery" on flip-chip-bonded ICs.
Daniel J. Ehrlich, president and CTO, Revise Inc.
Implementation of extended temperature range etching
The old ideas for thermal limits in plasma etch processing — that the wafer needs to be kept within a narrow range of temperatures to avoid photoresist image degradation, for example, still apply for well-established fabrication applications like resist-masked gate etch. Now that the industry has adopted a set of new materials and new applications are being found for plasma etch tools, there is a need for extended temperature range plasma etching. Plasma etch tools and processes need to be modified, or developed, to cover a temperature range beyond the classical 20-80°C span that has served well for many years.
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Where are the applications needing extended temperature ranges? FeRAMs and advanced DRAMs use materials like Pt, Ir, BST, SBT, and PZT. There has been a flurry of recent work on using high etch temperatures — on the order of 350°C — to improve both the etch profile and the etch rate of such materials. With commercial FeRAM structures now at 0.35—m feature sizes, and advanced DRAM development being performed with dimensions approaching 0.1—m, it makes sense to implement high-temperature wafer chucks using electrical resistance heaters or radiant heating elements. On another front, the recent growth of telecom applications means that InP-based optoelectronic devices are being made in volumes like they never have before. InP is an intermediate material, in that its best plasma etch results are obtained at temperatures around 200°C. Electrical resistance heaters, or other schemes, might be used to elevate the wafer temperature during etch.
Since these extended temperature range etches have the purpose of increasing etch rates, or making etch profiles more vertical and CD losses smaller, wafer temperature monitoring and control become more critical to the process beyond merely ensuring that the resist mask doesn't melt. Direct measurement of wafer temperature (not wafer chuck temperature) is essential to implementing any kind of effective closed-loop temperature control.
James D. McKibben, VP, worldwide marketing and sales, Tegal Corp.
ETCH
Critical etch advances at every roadblock
When new materials are being developed, the focus seems to be on the deposition processes, with the assumption that someone will figure out how to etch them. (The situation is somewhat reversed, however, in some applications, with the advances being driven by new etch capabilities. See, for example, "New capabilities with 3-D laser etching.")
The industry is currently meeting a variety of etching challenges for several new materials and increasingly stringent process control requirements.
Etching high-k gate dielectrics
High-k dielectric materials are being developed to replace SiO2 as a gate dielectric material because of scaling limits of SiO2, with tunneling currents and other effects becoming excessive in the nanometer range. Process control and metrology are also problems with the thickness required for SiO2 to continue to work as a gate dielectric. high-k materials allow a thicker gate dielectric, but their appearance at the 130nm and 100nm nodes on the ITRS creates significant etching challenges. For example, early endpoint detection systems are being developed because high-k gate materials (silicon oxynitride, silicon nitride, tantalum pentoxide, and barium strontium titanate) typically have higher etch rates than SiO2 [1]. An early endpoint detection system will detect the endpoint at a programmed depth before the gate electrode has cleared, according to Adrian Kiermasz, senior director of product management at Lam Research. At that time, the process recipe can switch to a very highly selective process that will not etch through the gate dielectric layer.
Etching new gate electrode materials
Similarly, polysilicon is reaching its scaling limit as a gate electrode material, with metals being developed as a replacement. According to Kiermasz, the initial metal gate to be implemented will be tungsten/tungsten nitride on poly, which is being introduced at the 150-100nm technology nodes. Tungsten is typically etched with fluorine chemistries, but these also etch gate dielectrics and the substrate in these applications. A likely solution is a combination of fluorine-based chemistry and the traditional chlorine/hydrogen bromide polysilicon etch chemistry. Mixing of fluorine and chlorine chemistries in the same chamber creates a need for well-controlled chamber wall conditions through in situ plasma cleans of the chamber between each wafer [2]. As always, process control strategies like this are critical to enabling the progress dictated by the Roadmap.
The challenges will continue as high-performance CMOS technologies require optimal gate electrode materials for NMOS and PMOS devices. The metal work function of the gate electrode material must be positioned within the channel's doped-silicon bandgap. Metals being explored for NMOS include tantalum, zirconium, hafnium, and titanium, while the metals being considered for PMOS are platinum, iridium, nickel, manganese, and cobalt. Etching of such dissimilar and rather noble metals will be a challenge, and the processes will likely be quite physical in nature and at relatively high temperatures [3]. (See "Implementation of extended temperature range etching" for further discussion of high-temperature etching.)
Etching low-k dielectrics
The major categories of materials being pursued as low-k intermetal dielectrics include organosilicate glasses, organic polymers, porous organics, and porous inorganics. The organic polymers require an oxidative or reductive chemistry that does not react with the copper. The organosilicates require a more physical etch component, while providing good selectivity to the barrier layer. Since many device technologies need in situ processing with several process steps, medium plasma density sources are better suited to this because of the ability to tailor the process to a wide range of materials, according to Lam's Kiermasz. — J.D.
References
- A. Perry, "Interferometry for Critical Etch Endpoint," Semicon Korea Technical Symposium Proceedings, 2000.
- S. Morishita et al., "Plasma-Wall Interaction in Dual Frequency Narrow-Gap Reactive Ion Etching Systems," Japan Journal of Applied Physics, Vol. 37, p. 6899, Dec. 1998.
- Y. Yunogami et al., "Anisotropic Etching of RuO2 and Ru with High Aspect Ratio for Gigabit Dynamic Random Access Memory," Journal of Vacuum Science Technology B, Vol. 18, No. 4, p. 1911, July/August 2000.
DUAL DAMASCENE/DIELECTRIC INTEGRATION
Challenges continue for Cu/low-k
Significant progress has been made in copper metallization and low-k dielectrics, with many announcements of milestones in 2000. IBM's April revelation of six-layer dual damascene Cu with Dow Chemical's SiLK was a big step, as was Sematech's March announcement of dual damascene Cu integration with materials such as Black Diamond from Applied Materials.
At Semicon Southwest in October, though, the news was primarily about the difficulties being encountered with integration of low-k materials in 0.13—m technology. The main problem was mechanical robustness during CMP.
 Figure 1. The Cu lines are at the same height, reflecting the absence of erosion with the Ultra SFP electropolishing system from ACM Research. |
(See "low-k integration issues" for a discussion of some other ongoing challenges.) The copper interconnect itself is also facing CMP problems such as dishing. Karey Holland, VP of technology at CMP pad supplier Thomas West Inc., puts it succinctly: "Right now no one is happy with the copper process."
Some voices in the industry have a brighter view, though, of the performance of low-k materials in CMP. Mike Thomas, the CTO of the Wafer Fabrication Materials unit of Honeywell Electronic Materials (HEM), reports that its aerogel Nanoglass is strong enough for CMP and has a dielectric constant down to 2.1. HEM is also promoting a stacked low-k structure with organic and inorganic materials that can be spin-coated using the same tool, claiming better electrical performance than any CVD approach.
The debate goes on, though, with CVD touted by Trikon Technologies, among others. Trikon emphasizes the evolutionary approach of CVD SiCOH. "The CVD approach also allows in situ deposition of complete dual damascene dielectric stacks (barrier/low-k/etch stop/low-k/cap), giving a simpler and cheaper process flow than the spin-on alternative," says Keith Buchanan, process integration manager at Trikon.
 The Ultra ECP copper plating tool from ACM Research targets Cu plating needs through the 35nm technology node. |
Structural engineering for low-k and strength Ulvac is addressing the two main technical challenges (strength and decreased dielectric constant) with one innovative development. In early 2001, it plans to begin marketing a porous SiO2 film made with 3nm vertical hexagonal columns — a "honeycomb" structure. This is stronger than competing materials, with a compressive strength of 16.7GPa compared to about 5GPa according to Ulvac, and the porosity gives it a dielectric constant of 1.5-2.0. If its 2001 introduction is successful, it would be about five years ahead of the ITRS prescription for dielectric constant. Moisture uptake is a potential concern with the material, but the vertical pore structure is inherently resistant. It is hoped that a standard cap layer will be all that is needed.
 Figure 2. Global planar copper deposition with NuTool's system. The planar surface allows a lower-force CMP process, suitable for low-k dielectrics. |
Eliminating CMP?
A radical approach to the difficulties of CMP of dual damascene structures has been introduced by ACM Research. The Fremont, CA, start-up is developing tools that — if successful in a production environment — will eliminate the need for CMP. Instead of planarizing structures with the largely mechanical action of CMP, a precise electropolishing system is used to remove unwanted material layer by layer. This results in what David Wang, ACM president and CEO, has termed "stress-free polishing" (SFP) on ACM's Ultra SFP tool. The process is slurry-free with no consumables and no pad issues, resulting in a cost-of-ownership of just $2/wafer, according to ACM CEO Wang.
It had been previously thought that electropolishing could not be used on very thin films, and one problem was polishing uniformly across the whole wafer. ACM figured out how to control the electropolishing current in different areas of the wafer, which allows the uniformity required at this scale. Figure 1 on p. 78 shows the lack of erosion over a set of Cu lines polished with SFP. Wang claims that Ultra SFP "can polish Cu supported by low-k dielectrics with k value less than 1.8," such as Xerogels. ACM is also developing a Cu plating system that uses a similar local control approach to plate Cu on seed layers as thin as 50Å, a capability that will take the technology to the 35nm node in 2013.
Simultaneous plating and polishing
A similar approach was introduced in 2000 by NuTool Inc., another Bay Area start-up. Homayoun Talieh, president and CEO of NuTool, describes his process of global planar copper deposition as "applying a conductive material from an electrolyte to a predetermined area of a wafer and preventing the accumulation of the conductive material to areas other than the predetermined area by mechanically polishing the other areas while the conductive material is being applied."
The result is a copper surface at essentially the same height independent of the underlying topography (Fig. 2). This allows a lower-stress CMP process that is more appropriate for low-k dielectrics, and it could conceivably eliminate CMP as well, matching ACM's goal. —J.D.
Low-k integration issues
Manufacturers and suppliers are striving to bring maturity to low-k/dual damascene for integration into high-speed 0.13—m devices. Previous feasibility issues concerning the integration of 2.5<k<3.0 dielectrics, such as film adhesion under CMP stress, photoresist poisoning during trench patterning, and preservation of bulk k values during post-etch treatment, have been understood and/or circumvented.
Now that these initial integration roadblocks have been managed, the new trend lies in extension of the bulk dielectric (whether organosilicate glass, OSG, or spin-on dielectrics, SOD) to 0.10—m devices. Extending the bulk dielectric requires a commensurate shift to SiC from SiN for the barrier, and elimination of the etch-stop layer defining the bottom of the trench. Removal of the etch-stop layer affirms the critical nature of the etch process in defining the line CD, especially with trench depth as an added source of variance to CD control. The etch process must now exhibit spatial uniformity of <6% (3s) across the wafer, including dense and isolated features. Feasibility in volume manufacturing requires the codevelopment of an etch depth sensor for endpoint detection by depth, on trenches of <180nm lateral pitch.
Reducing the bulk k of low-k dielectrics (OSG, SOD) and introducing new materials to meet <0.10—m requirements dictates module-level testing of multiple sequential processes to ensure past integration roadblocks do not resurface. One case in point involves the preservation of the bulk k value after integration. Isotropic O2 plasma, used for resist removal in dual damascene process flows, results in a significant increase in line-to-line capacitance when applied to spin-on OSG, or porous OSG damascene structures. The recognition of this trend though module-level testing has resulted in the adaptation of an anisotropic, non-O2 process on a capacitively coupled etch reactor for resist removal on k2.4 dielectrics. Clearly, as the ITRS technology roadmap creates more stringent challenges, a module approach will be required to ensure the precise inputs and outputs required for success.
Gary Hsueh, product marketing manager, Etch Products Business Group, Applied Materials
LITHOGRAPHY
Integrated imaging a key approach to optical lithography at 100nm+
John S. Petersen, president, Petersen Advanced Lithography Inc., Austin, Texas
The slow development of nonoptical next-generation lithography (NGL) techniques and the acceleration of the International Technology Roadmap for Semiconductors forces optical lithography to carry our industry farther into the realm of subwavelength-sized features. Over time, lithographers have developed a host of optical extension techniques. The earliest included shrinking exposure wavelength and increasing exposure system numerical aperture (NA). To extend resolution for at least small-pitch line-space features, the next step was to increase partial coherence. These early strategies lead us to 193nm exposure with NAs >0.6 and partial coherence of 0.85, to 157nm, and, possibly, to 126nm. Along the way, other techniques such as off-axis illumination (OAI), phase-shift masks (PSMs), and optical proximity compensation (OPC) were added to our lithography toolbox.
These tools have had limited use. Lack of infrastructure makes them expensive. Lack of technical maturity causes them to be used indiscriminately and incorrectly. Now, since NGL is still a few years away, we need all of these tools if we are to make the immediate generation of 130nm and smaller devices. Advanced lithographers are demonstrating how to make optical meet our needs for subwavelength imaging by combining layout, mask, exposure tool, resist, substrate, and pattern transfer into an integrated imaging system. Recognizing that this integration must occur, suppliers are forming alliances to create integrated systems that can be delivered to the customer intact. Our efforts have brought us to a point where we can decide whether to extend to 193nm or stay with 248nm exposure. Our choice will be pitch- and layout-driven and will be based on the technical robustness and our trust that a given integrated imaging system's technology is production-ready when we need it.
Mask
There are two major categories of integrated imaging systems. One uses strong PSMs with on-axis illumination, the other weak PSMs with off-axis illumination. Strong shifters are problematic because they are difficult to lay out. Most designs do not lend themselves to clean phase assignments; often unwanted phase edges appear because there is no clean terminus of the phase-shifting structure, necessitating a second trim-mask exposure. Weak shifters are easier to lay out, but require off-axis illumination and large NAs to attain the desired result. Overall, weak shifting is easier to implement, especially with very high transmission PSMs. It also offers larger packing density than the trim-mask approach.
Our work with a 248nm exposure tool and reticle enhancements shows that multiple-pitch 100nm lithography with 0.4—m depth of focus and >6% exposure latitude is attainable with 248nm exposure using a 0.7NA lens with off-axis illumination and properly tuned high-transmission masks (see figure). Using the same technique, extension to smaller features is also possible; our 248nm work suggests adequate image contrast to 70nm gates with similar process latitude. This approach uses scattering-bar assist features and biasing of high transmission weak shifters. Scattering bars are critical because they apply OPC, make it possible for isolated lines to be imaged properly with
OAI, reduce the mask error enhancement factor (MEEF), and dampen the effects of exposure tool aberrations.
MEEF is the key limitation to any of these techniques. Our work strives to maintain MEEF to <2. The primary issue in choosing between 248nm and 193nm wavelengths is that manufacturing, inspection, and repair infrastructure need to be developed for each phase-shift mask type. For the moment, 248nm gets the nod.
Exposure tools
NAs of 0.70-0.85 will allow extension on 248nm exposure to the 70nm node for line features and for isolated contacts, provided aberrations are minimized in a way that best matches the type of imaging being done and flare is minimized and strictly controlled. Beyond this, our continued forecast of minimum numerical aperture and exposure wavelengths needed to attain each technology node (see table) assumes liberal use of the optical extension toolbox. The values in the table assume two-beam imaging either with strong shifters or with high transmission weak shifters with dipole illumination. Apertures greater than 0.85-0.87 are used as the imaging technology terminus region.
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Experimental focus-exposure process window for 100nm lines imaged using 248nm 0.7NA ASML/700 with 30% off-axis Quasar illumination. Using 100-10,000nm pitches, the common process corridor (red oval) is 0.4—m depth of focus with >6% exposure latitude. Courtesy of ASML MaskTools
Based on 1999 ITRS forecasts, and assuming a single exposure process, this table shows that 157nm is needed for the 100nm node for contacts in 2004 and can be used through a large part of the 70nm era. Then 126nm exposure or NGL must be ready. Of course, with multiple exposure-stitching techniques, contact resolution could be extended to nearly half of the stated limits. Without stitching, 193nm will be needed for aggressive contact pitches. For 100nm gates, either 248nm or 193nm exposure will work. Since 248nm is more mature, however, and, considering continued "Fickian" evolution, it appears for the moment to be the stronger candidate for this node.
Layout and substrate
The substrate (i.e., the wafer and its layers) must be considered a critical part of the integrated imaging solution. Uncontrolled reflections and topography of the optical stack can destroy all enhancements to the aerial image. At the gate level, the components of the optical stack must be understood and balanced to minimize reflections normal to the surface and, because of the large NAs, at the oblique angles of the incoming light. These reflections deteriorate the latent image that forms in the resist during the exposure. Further, substrate photoreactions must be minimized to prevent device damage and negative interactions with the photoresist. This has been a persistent problem with chemically amplified resists on nitride substrates at 248nm. To control surface effects, photo-unobtrusive antireflection coatings must be identified and substrates will need to be planarized.
Besides topography, ultimate resolution requires strict adherence to orientation of features. All critical structures should be "Manhattans" at 0° and 90°, leaving enough real estate for adding gate-end assists.
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Resist
Absorption, outgassing, unwanted cross-linking, and masking are some but not all of the important resist attributes. Eliminating interference effects, containing chemistry to the exposed areas, and minimizing resist contamination by bases from the environment and substrate are paramount to success. Eliminating interference is done using an antireflection strategy that includes balancing resist absorbance so it is 0.4-0.45% at its desired thickness. Thinner films exposed with high NAs need to be in the upper part of this region for optimal performance. Containing chemistry is accomplished through diffusion well formation. This well allows the acid to move and react with minimal intrusion into the low-dose regions of the latent image and minimizes imaging bias contribution from diffusion. Imaging bias from develop must also be minimized, and any necessary biasing should be accomplished with OPC and exposure tool modification. All resist systems have some level of bias; as with any other imaging technique, it needs to be quantified and fed back up the chain to the layout and maskmakers so OPC strategies can be used more effectively.
Finally, line-edge-roughening (LER) of resist edges must be minimized to improve CD control. Martha Sanchez et al. of IBM showed that LER magnitude depends on the contrast of the image and the nature of the resist chemistry. Today, 248nm resist performance is more powerful than resists for 193nm and buys you more effective NA.
Advanced lithography is the process of building an integrated imaging system that synergistically applies design, mask, stepper, resist, substrate, and pattern transfer. At the 100nm node, we will need all of these with their image enhancement capabilities engaged, whether we use 248nm or 193nm lithography. For a 2003-2004 insertion, cooperation within the image infrastructure and with the users is critical. At this stage, little invention is needed, only engineering and money. If a wavelength is to be chosen for the node, however, 248nm is the current leader. n
Acknowledgments
The author thanks Fung Chen and Kurt Wampler of ASML MaskTools, Robert Socha of ASML, and Waiman Ng of KLA-Tencor for assistance in generating the high transmission weak shifter data, and FINLE Technologies for ProData focus-exposure analysis software. (A more detailed paper will be presented at SPIE's 2001 Microlithography conference.)