FIB technology keeps pace with process and packaging developments
12/01/1998
FIB technology keeps pace with process and packaging developments
Nicholas Antoniou, Micrion Corp., Peabody, Massachusetts
Engineers depend on sophisticated equipment, such as focused ion beam systems, to help them analyze circuit performance. A growing number of chips are now assembled using flip chip. Flip-chip packaging is, however, a serious roadblock to the established debug effort. The solution described here combines high-resolution optics, special chemistry, and hardware all integrated into one focused ion beam system.
Circuit modification (the rewiring of a chip at the circuit level) is a challenging but established application. Even though computer simulations have become very sophisticated, full evaluation of the functionality and performance of an IC requires a prototype built in silicon. Focused ion beam (FIB) technology can advance the evaluation process by exposing nodes that are inaccessible through external testing (see "FIB background" on p. 64). Once the evaluation is complete, changes to the layout of the chip are often necessary. The changes will require fabrication of new masks and samples, a process that takes weeks to complete. FIB technology permits engineers to bypass this costly and time-consuming process by rewiring an existing sample. They can then test changes without the need for new masks or silicon production, dramatically shortening the debug cycle, and allowing for a faster new-product introduction.
Advances in assembly technology introduced what seemed to be an insurmountable obstacle: flip-chip packaging. Instead of sitting face up, the circuit is mounted upside down in the package and is buried under hundreds of microns of silicon (Fig. 1). Recently, through innovation and years of development, FIB technology has not only overcome this obstacle, but has surpassed expectations.
Flip-chip testing challenges
Circuit modification has been likened to brain surgery for chips. This analogy has worked well with chips packaged using wire bond technology. The circuitry resides near the surface and is easily accessible through just a thin layer of material (the passivation). Although flip chips provide better electrical and thermal characteristics and higher pad count, they bury the circuit, making it inaccessible. Flip-chip packaging is thus analogous to attempting brain surgery through a patient`s feet: engineers have to remove hundreds of microns of silicon just to get near the circuit, a formidable but necessary task. In addition, flip-chip packaging is dominant in complex logic chips such as microprocessors. First silicon of such chips is, at best, in need of enhancement and at worst, in need of redesign. Since external test methods cannot directly access all the nodes buried inside the circuit, engineers could not analyze their circuits. As a result, circuit modification of flip-chip parts almost vanished as a tool for rapid prototyping. No viable alternative was possible without major developments in existing technologies.
The solution
In order to keep up with all of these advances in packaging, FIB manufacturers have had to develop new hardware, new techniques, and also integrate several existing technologies into one FIB system.
Four major developments in FIB technology have enabled the same level of circuit access for flip chips as for wire bond assembled parts:
* an integrated camera with infrared (IR) detection capability;
* very fast silicon removal;
* a laser interferometer stage with 0.25-?m accuracy; and
* sophisticated end-point techniques.
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Figure 1. Conventional wire bond packaging vs. flip-chip packaging.
The backside of a chip is featureless and also relatively thick (500 ?m or more of silicon). This surface is totally invisible to the FIB. An IR microscope integrated inside the chamber of the FIB system (e.g., Micrion`s FIBCam) allows navigation through the backside of chips (Fig. 2). The microscope can also tie in with CAD layout data by locking to alignment marks on the chip. Operators of the system can then locate areas of interest on the chip without having to remove any material and risk incurring damage.
Adding optical microscopy capability to a FIB facilitates work with flip chips, highly planarized devices, and samples that are coated with polyimide or other organic material. Since the FIB can only image surface topography (with very shallow penetration), any sample that is flat on top will be invisible to the scanned ion beam of the FIB.
Fast removal of very large volumes of silicon to access circuits through the backside required the development of a high-current FIB column and a revolutionary gas delivery system. The beam current is increased to about 30 nAmp at a spot smaller than 1 ?m. As the beam scans across the area of interest, the introduced high-flux gas improves the milling rate. XeF2 gas is delivered all around the beam at a distance of a few hundred microns above the sample. The combination of the high beam-current density and high gas flux enhances the milling rate hundreds of times over a mill without any gas present, producing large trenches in bulk silicon in a matter of minutes (Fig. 3).
Optical navigation and fast removal of silicon are complemented by a stage guided by a laser interferometer to allow position accuracy of 0.25 ?m across 200 mm of travel. Higher accuracy is attained if travel is limited to 25 mm (about the size of the largest available die), an advantage for 0.25-?m technologies.
Finally, sophisticated end-point techniques provide control during the milling process. Since the established end-point method relies on material change for a noticeable change in signal, stopping a mill within the same volume of material is impossible. The new technique using the microscope as the depth-measuring device can control gross silicon milling to the desired thickness. Additionally, the optical microscope can be used to generate an optical-beam-induced current in the circuit that allows for accurate depth control as the beam approaches the active circuitry.
Applying FIB to circuit modification
Complete debug of a circuit can only be carried out using packaged parts, due to the electrical, thermal, and other characteristics of the package. Wafer-level testing is thus usually limited to basic functions. Using the developments in FIB technology that are outlined in the previous section, circuit modification and probe point creation on flip-chip parts are now routine. First, engineers must remove the lid of the packaged sample to expose the backside of the chip. Next, polishing the backside improves imaging and thins the sample for easier access.
< Figure 2. FIBCam image taken through 100 ?m of silicon. Field of view: 140 ?m. < Figure 3. A 100 x 200 ?m trench milled to a depth of 230 ?m in about 20 min. Using the optical microscope, engineers locate fiducials on the circuit to lock the circuit layout (using CAD navigation tools such as Knights Technology`s Merlin software) to the chip. A very precise micromotor controls the optical microscope, allowing accurate depth measurements in any area of the chip. The software then calculates the plane of the circuit and indicates depth for any x-y location in the chip. The process of modifying a flip-chip circuit or creating probe points for debug consists of four major steps: * Step 1 includes all the preparation work necessary to get close to the active circuitry. The sample is mechanically thinned and loaded in the FIB system, where the remaining silicon is locally thinned (over the circuitry of interest) to ~10 ?m. * During step 2, the FIB deposits a thin oxide at the bottom of the trench in the presence of a precursor gas. This oxide protects the volatile silicon from any future gas-assisted work using the FIB. * Step 3 involves exposing the nodes of interest. A CAD program locates each node that will be contacted or cut and navigates the FIB to that location. The FIB then exposes the nodes and deposits dielectric to cover and later re-expose the nodes that will be contacted for rewire or used as probe points. This step is necessary to avoid conductive shorts with the bulk silicon. * The final step in this process consists of exposing (for use as probe points; see Figs. 4 and 5), cutting, and connecting metal lines as is commonly done in FIB applications. Results show that the FIB is capable of contacting active regions of flip chips such as source/drain regions (Fig. 6). With additional refinements and development, accessibility to the circuitry of flip chips should surpass that of traditional wire-bonded chips. With the development of this application, design and product engineers can debug flip chips and even produce prototypes in a matter of hours. First, they test the part and analyze the results. The data collected from a tester is usually insufficient to locate or discover a problem. Using the FIB, the created probe points (windows into the circuit wiring) provide a close look into the inner workings of a circuit. Once a problem is understood, a design change is usually required; using FIB, it can be implemented directly on a chip. There are two benefits to this approach: tests of the circuit modification are possible without new masks or new silicon production, and a working prototype is created. This prototype can then feed the need for parts further down the evaluation chain, saving even more time in the introduction of a new product. Once the modification is confirmed, the plant can generate masks and manufacture new chips. Figure 4. A probe point created at the bottom of a 100 ? 100 ?m trench about 100 ?m deep. Figure 5. Cross section of the probe point in Fig. 4. Figure 6. A circuit modification using active regions. Conclusion FIB technology has kept up with advances in semiconductor processing and packaging technology by developing new hardware, new techniques, and by integrating several imaging technologies into one FIB system. The result is that FIB technology is now applicable where it was once impossible to use; flip-chip packaged parts, highly planarized chips (CMP), and coated samples are no longer inaccessible. This permits IC manufacturers to shorten their new-product introduction cycles and to better understand the performance of their circuits. n Acknowledgment FIBCam is a registered trademark of Micrion Corp. NICHOLAS ANTONIOU received his BS and MS degrees in electrical engineering from Texas A&M University. His MS thesis work was on imaging and evaluation of CMOS latch-up using photo-induced current. Antoniou has worked at Motorola Inc. as a yield enhancement and process integration engineer involved with the start-up effort of MOS-11, Motorola`s first 200-mm fab. He has also worked as a product engineer for a line of microprocessors at Ross Technology, where he supported the design and manufacturing teams and started a FIB service lab. In 1997, Antoniou joined Micrion as a product-marketing manager for FIB lab tools. Micrion Corp., One Corporation Way, Peabody, MA 01960-7990; ph 978/538-6700, fax 978/531-9648, web site www.micrion.com.
