Formation of ultra-shallow junctions by ion implantation and RTA
12/01/1998
COVER ARTICLE
Formation of ultra-shallow junctions by ion implantation and RTA
Majeed A. Foad, Dean Jennings, Applied Materials Inc., Santa Clara, California
Forming sub-100-nm junctions for source/drain designs in <180-nm devices requires optimized low-energy ion implantation and rapid thermal annealing to place dopants accurately and activate them without excessive diffusion. Boron ions were implanted at a range of low energies and implanted wafers were then annealed using various soak times, temperatures, and ramp rates. Junctions with depths of 30-70 nm (at 1 ? 1018 cm-3) can be formed with sheet resistance tunable between 200 and 900 W/n, using spike annealing at ramp rates up to 150?C/sec. Oxygen content in the rapid thermal annealing ambient is also an important factor in controlling both sheet resistance and junction depth.
As device CDs shrink to 180 nm and beyond, doped regions in the transistor, in particular the source/drain (S/D) junctions, are getting shallower [1]. Stringent control on the lateral diffusion of the junction is critical to reduce adverse effects such as punchthrough and short channel effect. Research shows that low-energy ion implantation and rapid thermal annealing (RTA) can routinely form ultra-shallow junctions, thus meeting the semiconductor industry`s requirements for technologies down to 100 nm.
Junction depth (cj) requirements for future device technologies fall within a range of values for each node - for example, 54 ? 18 nm for 180 nm down to 30 ? 10 nm for 100 nm - with fast logic devices requiring the shallowest junctions [2]. Sheet resistance (Rs) values for S/D extension implants are typically in the 200-800 W/n range, with the lower values again required by the fastest switching devices. The need for lower Rs implies higher annealing temperatures, making shallow profiles even harder to achieve.
Channeling of dopants into the substrate has a significant impact on dopant placement, and ultimately, junction depth. Our investigations of the channeling behavior of boron implants between 10 keV and 200 eV show that for the lowest energies (<500 eV), there is little or no difference between a 7? and a 0? tilt implant. This implies that using normal incidence implants for shallow drain extensions will not adversely affect junction depth. Comparing crystalline to pre-amorphized wafers, we found that crystalline wafers show greater channeling until the energy range reaches well below 500 eV. At approximately 200 eV, channeling behavior is similar for crystalline and pre-amorphized Si, implying that pre-amorphization is no longer required to reduce channeling. PMOS transistors with low-energy, boron drain extension implants showed excellent electrical characteristics, proving that this type of implant is a viable option for =180-nm CMOS.
We then explored the effects of conventional ("soak") RTA vs. "spike" annealing, complementing the low-energy implant work. The spike anneal, with its minimal soak time, appears superior in tuning both cj and Rs, producing ultra-shallow junctions with depths below 40 nm and sheet resistance below 300 W/n. Spike temperature is the most important factor in controlling Rs, while the ramp-up rate does not greatly affect the secondary ion mass spectroscopy (SIMS) profiles. There is no obvious advantage in using ramp-up rates above 100-150?C/sec. The spike method`s higher target temperatures result in better dopant activation, while the short anneal time limits intrinsic boron diffusion for shallow junctions. The presence of oxygen in the annealing ambient appears to increase dopant diffusion, leading to deeper junctions.
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Figure 1. Secondary ion mass spectroscopy (SIMS) depth profiles of 1-keV, 1 x 1015 cm-2 B, implanted in pre-amorphized Si, comparing B implanted in drift mode and differential mode, retarded from 2 keV. The differential mode implant shows excellent match with the drift mode implant, and has the added advantage of higher implant throughput.
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Figure 2. As-implanted profiles of a 5 ? 1014 cm-2 B implant into crystalline and a Ge pre-amorphized wafer for energies of a) 1 keV, b) 500 eV, and c) 200 eV.
Low-energy ion implantation
Development of a new generation of low-energy (down to 200 eV) ion implanters now enables doping at very shallow depths [3, 4]. For the implanter discussed here, the xR LEAP system, the beamline design encourages the transport of low-energy ion beams through implementation of an improved source with more efficient extraction optics, and a shorter beam length from the ion source to the wafer. Having a very short beam path is critical in transporting high beam currents at low energies onto the wafer, due to reduced beam loss from space charge blow-up.
Our implanter uses a differential mode, where it extracts the beam at a relatively higher energy, analyzes the beam, then reduces the beam energy for implantation. This is in contrast to the drift mode, where a beam is extracted and implanted at the same energy. The differential mode helps in transporting low-energy ion beams with currents in the multimilliampere range, and thus maintains high wafer throughput. Testing of both drift and differential modes showed excellent matching (Fig. 1), indicating good energy purity for the differential mode implant with the added advantage of significantly higher wafer throughput.
Effects of wafer tilt and pre-amorphization on channeling. Channeling behavior at low energies is an issue that affects implantation of ultra-shallow junctions because of its relationship to dopant placement. We performed a series of boron implants at energies between 10 keV and 200 eV for three conditions: a 7? tilt angle, a 0? tilt angle, and an implant into Ge pre-amorphized Si wafer [5]. The 7? tilt angle is routinely used to suppress channeling, while a pre-amorphized wafer generally inhibits channeling as well.
For 10 keV, the 0? implant was significantly deeper than the 7? tilt implant. The 7? tilt implant, however, still shows considerably greater channeling than the implant into an amorphous substrate. Implants at 2 keV show similar behavior, but with a smaller difference in profile between the two tilt angles.
For 1 keV and below, the energy is so low that irrespective of incident angle, a major fraction of the ions couple into the channels. Also, the relative amount of channeling at 1 ? 1018 cm-3 remains constant for the different energies when comparing crystalline and amorphous samples.
A pre-amorphization implant, optimized for low-energy boron implant, however, limits throughput, so it is important to assess its advantage relative to junction depth. Figure 2 shows a B implant at a dose of 5 ? 1014 cm-2 for 1 keV, 500 eV, and 200 eV. The tilt angle for this set of implants was 7?, with a 0? twist angle for the crystalline wafers. The Ge pre-amorphization implant used is optimized for low-energy B implants. The 1-keV implant shows considerable channeling, which decreases at 500 eV and 200 eV. One reason for the disappearing difference between crystalline and pre-amorphous at the lowest energies may be that the boron implant itself amorphizes the Si at these energies and doses [6].
These data indicate that wafer tilting is not an effective means of suppressing channeling at low energies (e.g., <1 keV). In fact, high tilt angles increase shadowing effects and may increase unwanted asymmetric device behavior. Although the tilt angle does not prevent channeling at energies below 1 keV, implanting into pre-amorphized wafers gives a shallower profile. However, for the lowest energies, such as 200 eV, a pre-amorphization step may not be necessary to reduce as-implanted junction depth.
For chipmakers using = 2-keV boron implants, pre-amorphization is an important step to consider for suppressing transient enhanced diffusion and shallow junction formation. Furthermore, they must optimize the pre-amorphization dose and energy for the desired boron implant energy, based on cj from SIMS profiles prior to the RTA step, and cj and Rs after RTA.
RTA
Soak vs. spike annealing. RTA is the optimal method to activate the implanted dopant in shallow junctions. A conventional annealing profile involves ramping up to a target temperature of 1000?C, with a soak time of about 10 sec, then ramping down to ~200?C at a rate of ~50?C/sec. Generally, ramp rates of =75?C/sec are favor able to reduce the total residence time at high temperature. This lowers both the transient enhanced diffusion and the intrinsic boron diffusion, providing better control of (
Using the RTP XEplus Centura system, we also investigated another temperature ramp profile called "spike" anneal, which utilizes higher ramp rates and reduces the soak time to ~1 sec.* This approach minimizes intrinsic boron diffusion, hence cj. Higher target temperatures can also be used to activate more of the dopants and thus obtain the desired Rs. This feature gives the user the opportunity to tune both cj and Rs to the desired targets for each technology node between 180 and 100 nm.
A typical spike temperature profile has a ramp-up rate of 150?C/sec. The system achieves a uniform temperature during the ramp-up and ramp-down phases by using six optical pyrometers that measure temperature across the wafer at a rate of 20 Hz. Accuracy is assured by in situ emissivity measurement and compensation at 20 Hz. For spike annealing, having a uniform temperature during the ramp phase is critical, because much of the thermal exposure occurs during the ramp.
Figure 3 shows a comparison between soak and spike annealing in crystalline silicon. A soak anneal at 1000?C for 10 sec gave a cj of 95 nm, at a concentration level of 1 ? 1017 cm-3, and a Rs of 306 W/n. A comparable Rs can be obtained using a spike anneal at 1050?C, but with a shallower cj of ~75 nm. On the other hand, a comparable cj can be obtained using a spike anneal at 1100?C, giving a Rs of 212 W/n, indicating better dopant activation. At extreme temperatures (e.g., 1150?C), the intrinsic boron diffusion coefficient is such that significant diffusion occurs even in a spike anneal leading to a 130-nm-deep junction and a Rs of 178 W/n.
Anneal ambient effect on cj. The presence of oxygen during annealing leads to oxide growth on the silicon surface. In a phenomenon known as oxygen-enhanced diffusion (OED), interstitial defects are injected into Si during oxide growth, leading to increased boron diffusion into the bulk Si.
To investigate the extent and effect of OED on shallow junction formation, we a set of implanted crystalline Si wafers with 8 ? 1014 cm-2 B at 1 keV, then annealed the wafers in various mixtures of oxygen and nitrogen. Resulting SIMS profiles showed that the shallowest junction was formed when the wafers were annealed in pure nitrogen. A monotonic increase in cj occurred with increased oxygen, indicating the occurrence of OED. Sheet resistance was higher for the pure N2 case than if a trace of oxygen existed in the anneal ambient, indicating a loss of dopant, presumably via surface evaporation.
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Figure 3. SIMS profile of 1-keV, 1 ? 1015 cm-2 B implanted in pre-amorphized Si using Ge. The wafers were annealed using soak and spike methods with a ramp-up rate of 75?C/sec.
In general, if cj increases, Rs is expected to decrease. In the presence of oxygen, however, although the SIMS profiles confirmed increasing cj, Rs measurements show that there is a minimum Rs for trace oxygen, followed by a monotonic increase in Rs as oxygen increases. This is due to the fact that as the proportion of oxygen in the RTA ambient is increased, the oxide thickness also increases. This can lead to either or both of the following:
* segregation of the boron implant to the oxide interface and/or
* incorporation of some implanted boron into the oxide.
In both cases, the boron dopant is rendered inactive, leading to an increase in Rs. The increase in the oxide thickness has been confirmed by x-ray photoelectron spectroscopy measurements.
So, to achieve shallow junctions with good activation, it is important to have firm and repeatable control over the oxygen content during the rapid thermal processing (RTP) step.
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Figure 4. a) SIMS profiles of 1-keV, 1 ? 1014 cm-2 B implanted into pre-amorphized Si. The wafers were spike-annealed at various temperatures using a ramp-up rate of 150?C/sec. b) SIMS profiles of 1-keV, 1 ? 1014 cm-2 B annealed at 1050?C at ramp-up rates of 75, 100, 150, and 200?C/sec.
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Figure 5. Threshold voltage behavior for two different implants and effective gate lengths between 1 and 0.1 ?m.
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Effect of ramp rates on spike annealing. Another set of wafers was Ge pre-amorphized, then was B implanted at 1 keV with doses of 1 ? 1014 - 1 ? 1015 cm-2. These wafers were spike-annealed at 900-1100?C using ramp rates of 75-200?C/sec in a nitrogen ambient. Recent studies reported high ramp rates to reduce the depth of shallow junctions [8].
A separate test using 150?C/sec ramp-up rate and annealing at 1000-1075?C gave more or less similar cj (33 nm ? 1 nm at 1 ? 1018 cm-3). We noted a significant advantage in decreasing Rs, from 849 W/n to 492 W/n, by using higher temperatures, indicating greater dopant activation. At 1100?C, however, the intrinsic boron diffusion is high enough to induce a deeper junction, 42 nm, even under spike conditions with a Rs value of 376 W/n. Figure 4a shows the effect of spike temperature on cj and Rs.
We also investigated the effect of ramp-up rates between 75?C/sec and 200?C/sec. Wafers annealed at 75, 100, 150, and 200?C/sec indicated that the junction depths were very similar, at 32 nm for the four cases, within the SIMS measurement error (Fig. 4b).
Higher ramp rates demonstrated a corresponding trend to higher Rs. This can be due to the fact that the total integrated time spent by the wafer at high temperature decreases with increasing ramp-up rates, thus activating fewer dopants. Examination of a spike-annealed wafer using high-resolution lattice imaging revealed a perfect lattice recrystallization after spike RTA throughout the region of the originally pre-amorphized layer and up to the native oxide.
PMOS transistor results. To test our experimental developments, we obtained electrical results from PMOS transistors fabricated with a reference process and an optimal shallow drain implant. Ten wafers were processed using a 0.18-?m CMOS flow with electron beam patterning of the gate polysilicon [9, 10]. The reference process used an 8-keV BF2 implant. For contrast, we also implanted wafers with 1- and 2-keV B, and with 3-keV BF2. All implants were in crystalline substrates. The implant dose was 3 x 1014 cm-2 with a 10-sec, 1000?C anneal, resulting in a 57-nm junction depth around the 1 ? 1018 cm-3 level.
All conditions showed working transistors with threshold voltage behavior and sub-threshold characteristics as expected. Figure 5 illustrates the threshold behavior for two implants: the reference 8-keV BF2 implant and a 1-keV B implant. The 1-keV B implant showed much improved roll-off behavior
We measured the transistor asymmetry by comparing drive current in forward and reverse mode, i.e., source and drain interchanged. The 8-keV BF2 reference process gives the largest asymmetry, averaged over transistors spread across the wafer (see table). There seems to be a tendency for better symmetry with lower boron energy, but additional data is required to confirm this trend. No significant difference in junction leakage was observed in gated diode structures, indicating that the level of damage and unwanted impurities around the junction was comparable for all implants.
Conclusion
Ultra-shallow junction formation is enhanced by a high degree of synergy between the ion implantation and annealing steps. An optimum implant-anneal process that combines low-energy (1-keV) implant and "spike" annealing by RTP enables formation of junctions with depths between 30 and 70 nm (1 ? 1018 cm-3 SIMS boron concentration) and tunable sheet resistance between 300 and 900 W/n. Such junction performance matches the requirements of device generations to approximately 100 nm.
For the implant step at the lowest energies, there is essentially no need for tilt implants, since normal implants do not adversely affect junction depth. Both crystalline and pre-amorphized wafers exhibit considerable channeling through the 1-keV to 200-eV ranges, but at 200 eV, channeling behavior is similar for crystalline and pre-amorphized Si, implying that pre-amorphization may not be required.
The technique of "spike" RTA with little or no soak time can produce junctions as shallow as 30 nm. The spike temperature is the key factor in controlling Rs, while ramp-up rate has little effect on junction depth. The spike annealing`s higher target temperatures result in better dopant activation, while the short anneal time limits the intrinsic boron diffusion, again enabling shallow junctions. In a test of the process, PMOS transistors with low-energy implants and RTA showed excellent electrical characteristics.
Acknowledgment
The authors thank A. Murrell, G. de Cock, E. Collart, D. Wagner, Y. Matsunaga, and D. Lopes for contributing to this work and for helpful discussions; and J. Schmitz, J. van Zijl, and J. van Berkum at Philips Research Laboratories in Eindhoven, The Netherlands, for the transistor data.
References
1. The National Technology Roadmap for Semiconductors, Semiconductor Industry Association, San Jose CA, 1997.
2. S. Moffatt et al., "Electron-volt, High-current Implants into Silicon SDR (Surface Damage Region) and the Effects of Anneal Time to Form 200-700 ?, Low-leakage Junctions," presented at IIT98, Kyoto, Japan, 1998.
3. M.I. Current et al., "200 eV-10 keV Boron Implantation and Rapid Thermal Annealing: Secondary Ion Mass Spectroscopy and Transmission Electron Microscopy Study," J. Vac. Sci. Technol. B16, pp. 327-33, 1998.
4. M.A. Foad, J. England, S. Moffatt, D.G. Armour, Proc. 11th Int. Conf. on Ion Imp. Tech., 1996, IEEE, p. 603, 1997.
5. Y. Matsunaga et al., "Effect of Surface Treatment During Ge+/B+ Two-step Implantation," presented at IIT98, Kyoto, Japan, 1998.
6. E.J.H. Collart, M. Heijdra et al., "Low-energy (0.1-10 keV) 11B+ Ion Implantation Damage Characterization Using Rutherford Backscattering Spectrometry," presented at IIT98, Kyoto, Japan, 1998.
7. Private communication with M.J. Caturla, Lawrence Livermore National Lab, 1998.
8. S. Shishiguchi, A. Mineji, T. Hayashi, S. Saito, "Boron-implanted Shallow Junction Formation by High-temperature/Short-time/High-ramping Rate (400?C/1 sec) RTA," VLSI Technology Tech. Dig., p. 98, 1997.
9. J. Schmitz, "Design and Characterization of High-performance 0.13-?m NMOS devices," Essderc `96 Conference Proceedings, Bologna, Italy, p. 301, 1996.
10. E.J.H. Collart, A.J. Murrell et al., "Characterization of Low-energy Boron Implants and Electrical Results of Submicron PMOS Transistors," presented at IIT98, Kyoto, Japan, 1998.
MAJEED A. FOAD received his BSc in physics, his MSc in chemistry, and his PhD in electronic engineering from Glasgow University. His thesis concerned the development and characterization of damage-free, dry-etching processes for deep submicron technologies, using electron beam lithography. During post-doctoral research at Salford University, he built a dual ion source, UHV, ultra-low-energy ion implanter using beam deceleration technology. Foad has held several positions at Applied Materials, including program manager for both charging and xR LEAP; he is currently technology manager in the Implant Division. He holds four patents and has published more than 75 scientific papers. Applied Materials Inc., 3050 Bowers Ave., PO Box 58039, Santa Clara, CA 95054-3201; ph 408/727-5555, fax 408/748-9943.