Global yield engineering for IC production
12/01/1998
Global yield engineering for IC production
E.A. Sack, Zilog*, Campbell, California
A comprehensive approach to yield engineering can identify hidden variables that have the greatest influence on global fab yield. Software macros were written to extract yield sensitivities more quickly from a common database. Rapid determination of sensitivities allows for more efficient application of engineering resources and improved global yield.
The process of getting the maximum number of good products shipped for every square inch of silicon started in the fab is defined as global yield engineering (GYE). Historically, yield engineering focused on reducing wafer scrap in manufacturing, shrinking the size of semiconductor die, and reducing defects. However, maximizing the number of good products shipped for every square inch of silicon started is more complicated. The product design, test strategies, and the process itself all interact in determining global yield.
A well-managed semiconductor fab holds the actual process parameters as close to the process design objectives as physically possible. Chips are designed such that yield is maximized for the modeled processes. However, the actual process parameters frequently differ from the models, and the computer-aided designs (CAD) never include all the subtleties of the process. Discrepancies are greatest when designs push the state of the art and/or include a high content of analog as well as digital circuitry.
Wafer manufacturing is a statistical process. In the past, one could count on a distribution of process parameters in the fab (Fig. 1a) such that some yield would be achieved even if there were a mismatch between the CAD "technology files" (the process parameters assumed in the design) and the way the fab was actually operating. Modern process equipment, however, significantly tightens the distribution of parameters in the fab (Fig. 1b), such that a theoretically perfect design and excellent process control could actually produce zero yield. While zero yield with a perfect design is rare, there is great need for better yield engineering techniques.
Systematic yield engineering.
Figure 2 shows the five major elements of IC manufacturing when viewed as a system. Compatibility between the CAD technology files and the way the fab actually runs is critical. The metrics in the wafer manufacturing process are subject to statistical process control (SPC), that is, each major process step is followed on a control chart and displays a predictable distribution.
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Figure 1. Conceptual representation of fab process parameters in a) a typical distribution, and b) in significantly tighter distribution with current equipment. The tighter distribution can, paradoxically, result in lower yield under some conditions.
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Figure 2. The major components of semiconductor manufacturing that can influence overall yield.
Wafers that come out of the fab undergo "process evaluation," in which test transistors (and other structures) are electronically interrogated to determine how closely the processing has adhered to the design objectives. Following process evaluation, wafers are probed and the die are either identified as good/bad or graded as to the likelihood that they will make good shippable end-products. Following dicing and packaging, the end chips are subjected to what is usually called "final test," and again identified as good/bad or graded in accordance with market conditions. Usually following final test, a quality control step retests samples of the outgoing chips to ensure proper binning.
In all of these IC design and manufacturing activities, a tremendous amount of data is collected. The SPC measurements (in the fab), the process-evaluation measurements (after the fab), the probe measurements, and the final-test measurements can easily add up to tens of thousands, if not hundreds of thousands, of data elements for each die. These data points, if examined at all, were usually used only to improve process control in one particular area; many data points were discarded and never utilized.
The primary objective of the Zilog GYE project was to maximize global yield using reasonably sophisticated computer techniques to optimize the interaction between the SPC, the process-evaluation, the probe, and the final-test parameters. A second objective was to feed information about the way manufacturing was actually running back into the technology files automatically, so that they always represented "the real world."
The basic mathematical concept employed (albeit tailored for digital computing rather than classical analytical analysis) is that of "partial differentials." The fundamental objective is to determine how the yield of good products out the door at final test varies with the attributes at a) the probe step, b) the process-evaluation step, and c) the individual SPC stations within the fab. Because of inherent complexities, we reduced the analysis (at least in start-up) to asking three yield questions:
* Which probe attributes are the most sensitive determinants of high final-test yield?
* Which process-evaluation attributes are the most sensitive determinants of high probe yield?
* Which SPC attributes are the most sensitive determinants of the process-evaluation parameters?
Theoretically, one could skip the intermediate steps and simply ask which SPC parameters are the most sensitive determinants of high final-test yield, but we felt that the whole organization would benefit by rigorously practicing yield engineering.
Global yield engineering system
The first step in the GYE system is to get all of the data that are collected in the fab into a single (or linked) database(s). SPC
parameters are typically collected either in individual pieces of fab metrology apparatus or in a central fab computer, while process-evaluation, probe, and final-test attributes are collected in individual tools. For the most part, these databases have been in different formats and were not easily linked in a master computing facility. Working with KLA Inc. (starting before the merger with Tencor), Zilog developed the technology to import these data collection files into a central computing facility, such that the entire test/measurement pedigree of every wafer (and, if desired, every die) may be retrieved from a single databank.
Associated with the challenge of gathering all of the data into a consolidated, addressable database is that of making it easy to manipulate the data. As is true in most semiconductor manufacturing companies, Zilog has a central yield engineering organization that interacts with design, process, and test engineering functions in the ongoing effort to optimize the yield of products shipped out the door. In Zilog, as we know to be typical of many chip manufacturing businesses, the design, wafer processing, and final-test facilities exist in different parts of the world. We felt that by giving the yield engineering function certain predefined "macros" to work with, they could more easily bridge the issues of space and time that always create difficulties in concurrent yield improvement activities.
The three main macros that were developed adhere to the "partial differential" concepts. Corresponding to the three yield questions defined above, the macros allow the yield engineer to determine quickly the most sensitive parameters in influencing the next level of yield. These macros do not preclude testing other interactions in the database, but they provide a start-up menu that, it is hoped, results in an orderly process rather than a random walk.
Yield engineering macros
Figure 3 illustrates the general form of the macros that were developed for the GYE model. The sensitivity analysis is conducted using the assumption that there are several sources contributing to variation of the dependent variable (such as final-test yield), and that these individual sources follow a normal distribution:
s2Total = s2a + s2b + s2c
where s2a represents across-wafer variation, s2b represents wafer-to-wafer variation, and s2c represents lot-to-lot variation.
When the model is applied, two important characteristics are generated. The first is the "F-value," defined as the ratio of the mean square for the model over the mean square for the error term (including both model and experimental errors). The F-value analysis determines the chance that the observed relation would occur randomly, and taking more data tends to allow smaller effects to be seen. We used F-values lower than 0.05 to verify models (i.e., <5% chance of seeing the effect randomly).
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Figure 3. Schematic showing the general form of the macros developed for the Global Yield Engineering (GYE) system.
The second characteristic is R2, the coefficient of determination. It is a value between 0 and 1 that shows the fraction of the total variation that is explained by the model:
R2 = (Sum of squares in model) / (Sum of squares total).
Figure 4 shows an example of the general macro. The "drain current-scribe line monitor N channel transistor" process-evaluation bin had the greatest influence on the number of good die at probe test. Similarly, the "threshold adjustment implant monitor-SPC" attribute had the greatest influence on the desirable "drain current-scribe line monitor N channel transistor" process-evaluation attribute.
By applying these macros, the yield engineer can quickly determine sensitivities and provide recommendations to Process, Test, and Design as to how to maximize the global yield. For example, Design may need to modify the product to remove a particular SPC sensitivity. Alternatively, Test may need to make some change in the process-evaluation or probe bin attributes, or Process may need to change the SPC targets in the fab.
With short IC product life cycles, and extensive requalification required for a new design, it may not be economical to redesign a mask set to correct for a particular SPC sensitivity. Historically, it was not practical to tailor recipes to products, since there were significant disadvantages in tool capacity and data entry. Fortunately, fab equipment processing recipes are now downloadable, and lot-specific recipe control can improve yield. We have arrived at the point where the process can be adjusted to fit the design, rather than the other way around.
This is not to suggest that Design should be encouraged to ignore process design standards. Good yield engineering still starts with the design technology files being as close a fit as possible to the actual process. GYE provides exactly the data required to optimize those technology files over time.
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Figure 4. GYE macro schematic relating the premium probe pass bin to the most significant process-evaluation bins. Another macro shows that the most important variable here (the drain current) was most influenced by the threshold adjustment implant monitor parameter of SPC.
Applications
Keyboard chip oscillator frequency. Maintenance of R/C oscillator frequency in a reasonably tight range is important to OEM keyboard manufacturers. Cost constraints usually do not permit the use of crystal or ceramic resonators. Final-test yields on a new keyboard chip were low and erratic, and inconsistent with the design model. GYE analysis showed that the model did not adequately take into account certain second order "fringe" resistances and capacitances; this new information enabled Design to fine-tune the model so that chip yields became consistently better than 95%.
TV chip drain current sensitivity. A new TV controller chip was yielding at approximately 50% of the fab defect density entitlement. Application of the GYE macros uncovered a significant yield sensitivity to a certain transistor saturated drain current, even though the drain current variation in the process was well within the CAD technology file design limits. The problem was quickly resolved by a design modification once the quantitative data was fed back from the fab to Design.
Modem chip speed sensitivity. Pilot lots on a new modem chip showed low yield to a critical speed parameter when manufactured in the center of the defined fab process. Application of the GYE tools revealed a strong correlation between effective channel length (in a process evaluation scribe line monitor) and final-test yield. In the short term, manufacturing was able to increase yields substantially by biasing the process toward the sweet end of the yield curve, while Design modified the path on the chip that was too slow.
Conclusion
Viewing yield optimization as a system involving Design, Process, and Test is not necessarily a new idea. However, the Zilog GYE system significantly enhances the yield engineer`s ability to capture the critical sensitivities from ongoing manufacturing data. These quantitative sensitivities allow fabs to resolve product yield problems quickly, while minimizing the time wasted in "debating" whether Design or Process should be responsible.
All of the manufacturing data should be maintained in one common data base. It is becoming clear in the practical application of the GYE process that the time will come when the CAD technology files must also become part of the same data bank.
Predetermined "macros" significantly speeded up the identification of the principal yield sensitivities between the various parts of the overall manufacturing system. GYE principles are valuable in both production ramping and sustaining, and they provide Design, Process, and Test groups with a common language that inevitably leads to a higher level of understanding. n
Acknowledgments
Afsaneh Azadeh at the Zilog Campbell, CA, facility and Dan Doyle at the Zilog Nampa, ID, manufacturing plant have been the project managers for this Global Yield Engineering project. They have been ably assisted by David Nuerenberg, who heads up the Nampa Yield Engineering activities, with inputs from many others at that facility, including Alan Shaw and Bill Lynn. KLA -Tencor Corp. has played a key role in the creation of the software that permits Zilog to take a broad global view of product yield engineering. I especially want to thank Theresa Hedger of the Zilog Office of the President staff for assisting me in the preparation of this article.
EDGAR SACK received his PhD in electrical engineering from Carnegie Mellon University in 1954. He was involved in the early development of IC technology during 15 years at Westinghouse Research Labs, eventually heading the IC division in 1967. He left to head the IC operations of General Instrument Corp., spent 16 years with the company, and was named a senior VP in 1977. He was later recruited by EXXON to head its Zilog operation. He can be contacted at his e-mail address: [email protected].