Dual damascene aluminum for 1-Gbit DRAMS
11/01/1998
Dual damascene aluminum for 1-Gbit DRAMs
Roy Iggulden,* Larry Clevenger,* Greg Costrini,* David Dobuzinsky,* Ronald Filippi,* Jeff Gambino,* Chenting Lin,** Florian Schnabel,** Stefan Weber,** IBM*/Siemens** DRAM Development Alliance, Hopewell Junction, New York
Lynne Gignac, Maria Ronay, IBM-T.J. Watson Research Center, Yorktown Heights, New York
An advanced four-level interconnect process with three levels of minimum pitch (0.35 ?m) dual damascene wiring is illustrated in this article. This novel process sequence is designed for a 1-Gbit DRAM (0.175 ?m generation), and provides up to a 10% saving in chip area over a conventional three-level scheme. The electromigration and stress-migration performance of dual damascene Al is far superior to that of traditional RIE Al, alleviating the need to use Cu for improved reliability.
Important factors for DRAM on-chip interconnect design are low cost, extremely low contamination levels, tight pitch wiring, and low capacitance in the bitline. In comparison to a back-end of line (BEOL) interconnect process optimized for logic, where line resistance is a major factor, a process optimized for memory does not focus on line resistance. For this work, Al was chosen over Cu because of its superior compatibility with previous technologies, its material maturity, its limited contamination issues, and its cost effectiveness.
As VLSI chip features are scaled to the 0.175-?m regime, numerous challenges arise concerning conventional BEOL processes. Dual damascene (DD) was developed because it eliminated the need for metal etch and oxide gap-fill, lowered the number of processing steps in the BEOL, lowered the overall product cost, and avoided problems associated with lithographic overlay tolerance.
DD approaches offer the following advantages over conventional subtractive schemes that reactive-ion etch (RIE) blanket metal: lower cost, self planarization, relatively simple etches, high aspect-ratio metal fill instead of oxide fill, and superior reliability of the metal lines [1-5]. Furthermore, if Cu is eventually required for future DRAM generations, Al DD provides an evolutionary path for Cu DD. When using Al DD, the most critical items are the oxide patterning, the reduction of topography caused by Al CMP, and the filling of high-aspect-ratio vias by an Al metallization scheme that does not degrade any underlying metal levels [6].
Process flow
The DD process begins with a single oxide deposition serving as the inter-level and inter-metal dielectric. The oxide thickness was chosen to provide the proper wire thickness after Al CMP oxide erosion, and to ensure that the via is significantly thick below wide wiring features. Vias are defined by DUV photolithography and an etch stopping on the underlying metal. Wires are then defined by DUV photolithography and a timed etch stopping in the oxide. In other scenarios, the wire can be etched first or a hard mask can be deposited as an etch stop between the via dielectric and the wire dielectric. The via/wire recesses are then filled using a multistep metallization process. The wires are isolated and planarized using a noncorrosive Al CMP process; this completes the dual damascene process flow, leaving a planar surface for the next wiring level to begin (Fig. 1).
The first three metal levels (C1/M1, V2/M2, and V3/M3) consist of DD structures (C = contact, V = via, and M = metal line). The DD processes begin with the deposition of a SiO2 dielectric layer for both the contact or via level and the wiring level. First, the via is etched with a process that is selective to metal. It has a top diameter of 0.22 ?m. The line is then etched in a timed process exhibiting a minimum pitch of 0.35 ?m in the memory arrays. The lithography for both lines and vias is accomplished with 248-nm DUV exposure, off-axis illumina tion, and proximity corrections. The oxide etches use fluorinated hydrocarbons.
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Figure 1. SEM cross-section of a four-level interconnect system for 1-Gbit DRAM production, featuring dual damascene aluminum metallization.
Subsequently, the metal is deposited into the DD structures. A two-step metal CMP process is used to achieve planarization after the deposition, with the first step used to remove the Al or W and the second step used to remove the liners. The C1/M1 level is lined with nitrided Ti and then filled with a CVD W process, and the V2/M2 and V3/M3 levels are filled with an Al metallization scheme. Another SiO2 dielectric is deposited onto the polished M3 wiring for a via (V4) level only. A slightly tapered contact is then etched with a 0.35-?m bottom diameter and a 0.50-?m top diameter. A Ti/TiN/AlCu/TiN deposition is performed in order to fill V4 and blanket the wafer surface. Metal lines with a 1.4-?m pitch are patterned into this blanket film by a RIE process to form the last metal line in the four-level scheme.
Dual damascene etching
Many different methods of forming DD patterns in SiO2 are available. One can begin with either the patterning of the interconnects or the vias, and various hard mask schemes may be employed. In these four-level structures, the via lithography and etch is carried out first, followed by the interconnect lithography and etch. This process flow has the advantages of performing the more difficult via lithography and via antireflection coating (ARC) etch on a planar surface. Also, the ARC and resist of the subsequent line lithography fill in the via holes, providing a fairly planar surface for line exposure.
Developing a via-first DD etch sequence (the via formed prior to the line for a given level), however, required the resolution of a number of critical issues relating to the line patterning. Due to an organic ARC spun onto the wafer and into the vias prior to the line lithography, etch residues tend to remain in the via after the line etch [2]. Such a residue, sometimes referred to as a fence, can cause problems for metal filling and reliability (Fig. 2a). Increasing the ARC open etch time and O2 flow decreases the amount of fence formation (Fig. 2b). Too much increase in the ARC open etch time, however, can cause the sidewalls of the lines to roughen, and too much of an increase in the O2 flow will increase the width of the lines and cause leakage between interconnects [2].
Metal deposition
Al dual damascene metallization sequences stem from a basic process flow: degas/sputter clean/wetting and contacting layer/barrier layer/cold seed layer/hot bulk layer. The initial layer wets the oxide and metal surface in the trenches and vias, and acts as a getter to absorb any contaminants at the via bottom. The barrier layer curbs the formation of undesirable intermetallic compounds that increase contact resistance and can lead to device failure. The seed layer coats the liner with a thin conformal base to enhance surface diffusion during reflow. The bulk Al fills the structures at elevated temperatures; the optimum temperature provides enough reflow for void-free fill while limiting intermetallic formation.
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Figure 2. SEM cross-sections showing a) a fence in the V2 level, andb) the lack of fences in the V2 level and a fence in the V3 level resulting from the improved litho/etch process.
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Figure 3. Percentage of continuous via chains for a standard reflow process vs. the advanced CVD/PVD process.
Initial Al dual damascene metallizations included three liners (wetting, barrier, and seed layers) deposited by standard PVD, collimated PVD, or PVD with a longer target-to-substrate distance. The filling of DD structures by conventional PVD Al techniques, including reflow at elevated temperature, is marginal for feature sizes smaller than 0.25 ?m and aspect ratios greater than 2.8:1.
Many advanced metallization techniques were investigated, including ionized PVD, advanced magnetron PVD, high-pressure fill, and a CVD/PVD process. The CVD/PVD process was the most robust of the options, with the best electrical results, the best reliability, and the most extendibility. It reliably fillsstructures down to 0.175 ?m and aspect ratios up to 4.5:1. A comparison of chain yields is shown in Fig. 3 for a PVD Al reflow (directional Ti/directional cold AlCu/hot AlCu) process and the CVD/PVD Al process.
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Figure 4. TEMs of a) PVD Al reflow (Ti/TiN/cold AlCu/AlCu >410?C) and b) CVD/PVD Al (Ti/CVD TiN/CVD Al/PVD AlCu <410?C), showing the latter process avoids TiAl3 formation.
The CVD/PVD process sequence is degas/sputter clean/ionized-PVD Ti/CVD TiN/CVD Al/PVD AlCu (0.5 wt%). The ionized-PVD Ti liner provides good bottom coverage and moderate sidewall coverage at a thickness no greater than 40 nm. The CVD TiN liner provides excellent conformality and good barrier properties at a thickness =10 nm. The CVD Al liner provides excellent conformality and good wettability at a thickness =100 nm. The PVD AlCu deposited at a temperature <430?C provides a final metal stack with void-free filling and minimized intermetallic formation.
An important consideration when using two levels of Al DD is the effect that subsequent metal depositions have on the underlying metal layers [6]. In particular, if the temperature treatment exceeds ~430?C, then an increase in sheet resistance of underlying Al levels is observed [7]. The CVD/PVD low-temperature process shows no shifts >10% in the sheet resistance of any level. One of the main causes of increased sheet resistance is the formation of TiAl3 in the metal lines and vias. The new CVD/PVD process strongly suppresses TiAl3 formation, compared to a standard Al reflow process (Fig. 4) [7].
Aluminum CMP
Al CMP involves a two-step process where the first step removes the blanket Al and the second step removes the liners. It is also feasible, however, to have a one-step Al CMP that accomplishes both Al and liner removal. Al CMP requires a metallization with reasonable thickness uniformity and good adhesion to the underlying films.
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Figure 5. Electromigration of RIE Al vs. the advanced CVD/PVD dualdamascene Al process.
In a typical two-step Al CMP process, the first slurry passivates the metal surface while the applied mechanical force along with friction polishes away the passivated metal. Topographic variation is minimized because the high points are subjected to a greater applied mechanical force than the low points, and removal rate is proportional to the mechanical force. Once the passivated top layer of metal is polished off and removed from the surface, the underlying metal is passivated and the process continues until the blanket Al is removed.
After the majority of Al is removed from the field regions, a second slurry is introduced that passivates and removes the liners (Ti and TiN). This second polishing step continues until the oxide is slightly eroded, to ensure that the field regions are cleared of all residual metal. The wafer is then cleaned to remove residual particles and chemicals.
Al CMP is a critical process step, especially in a scheme involving multiple Al DD levels. Problems at the upper levels arise because of the residual topography that is typically introduced during the polishing of the preceding levels. The maximum amount of topography an embedded DD layer can add without causing severe problems is approximately 150 nm.
The improved CMP for embedded Al requires a slightly increased polishing time, to minimize the topography that can produce line shorts on the second Al level. However, an increased polishing time also increases the line resistance, since the effective cross-sectional area of the Al portion of the interconnect line is reduced by a combination of metal dishing and oxide erosion. This tradeoff between the sheet resistance and shorts yield can result in a small process window. Hence, the polish process should be designed to create minimal topography at lower levels.
Reliability
In general, high-quality, void-free filling combined with a good liner/Al interface maximizes mean-time-to-failures in electromigration stress tests. The mean-time-to-failure of the Al DD structures filled with the advanced CVD/PVD process is nine times greater than structures formed with a conventional Al RIE process (Fig. 5), and is similar to the reliability of the Cu damascene BEOL scheme recently reported [8]. Furthermore, the mean-time-to-failure of a DD structure filled by a standard Al reflow process is similar to RIE Al [1].
Conclusion
A novel four-level BEOL DRAM process with three levels of minimum-pitch dual damascene wiring has been developed. The four-level scheme saves chip area, allows for packaging transfer from the previous generation, and is cost effective. The advanced Al metallurgy fills all the needs of a memory device by having low cost, low contamination, material maturity, and the ability to fill tightly pitched lines. In addition, the reliability of the advanced Al is far superior to that of RIE Al and to that of alternate Al DD processes, and approaches that of Cu. n
References
1. T. Licata, et al., VLSI Multilayer Interconnection Conf., 596, 1995.
2. R.F. Schnabel, et al., Microelectronic Engineering, 37/38, 59, 1997.
3. R.C. Iggulden, et al., VMIC Conference, 49, 1997.
4. K. Kikuta, T. Nakajima, K. Ueno, T. Kikkawa, International Electron Devices Meeting Proc., 11.7.1, 1993.
5. K-Y. Lee, S-C Lee, Y-W Kim, Japanese J. of Applied Physics, 35, 1940 (1996).
6. S.J. Weber, et al., Thin Solid Films, 10586, 1998.
7. L.M. Gignac, et al., ULSI Conference, 1997.
8. S. Venkatesan, et al., IEDM Conference, 1997.
For more information, contact Roy C. Iggulden, Metals Unit Process Engineer, IBM Microelectronics, ph 914/892-9021, fax 914/892-9068, e-mail [email protected].