Wafer-level burn-in will cut times and cost

11/01/1998

Wafer-level burn-in will cut time and cost

Motorola Semiconductor Products Sector and Tokyo Electron (TEL), with the help of W.L. Gore and Associates, are on track to be the first in the semiconductor industry to qualify wafer-level burn-in processing - burn-in testing of ICs while still in wafer form. This new technique is expected to cut conventional IC manufacturing cycle time by up to 25% and direct manufacturing costs as much as 15%. And, it is likely that the new technique will reduce new-IC development time and future capital investments in manufacturing capacity. Bill Walker, senior VP and director of sector manufacturing for Motorola, Austin, TX, says, "This process will dramatically change the layout and process flow of wafer manufacturing and assembly facilities. It also represents a major step toward improvement of our overall manufacturing cycle time."

Recently, there has been increasing interest and effort in the industry to fold "singulated-IC" back-end operations into the back of the front end (i.e., wafer fab), for the very cost effectiveness that the Motorola-TEL-Gore process now promises. Indeed, this announcement has piqued the interest of - and beat similar development work at - Microelectronics Computer Technology Corp., Austin, TX, and Texas Instruments.

Motorola`s new process (see figure) is advantageous for both packaged and bare-die products, but savings are most dramatic for producing known good die where loading and unloading to carriers and two test operations are eliminated.

Terry Higashi, CEO and president of TEL, says, "This development will become a key technology for revolutionary improvement in the back end of semiconductor production." With wider adoption of wafer level burn-in, Higashi foresees prompt, rapid improvement in the efficiency of the back-end wafer test process and acceleration in distribution and application of known good die and wafer-level bumped ICs. Both trends could further reduce the reliance on packaged ICs in many microelectronics applications.

While this new technique is applicable to all types of semiconductors and packaging methods, it was initially designed to test ICs that use flip chip or "bumped" interconnect technologies typically associated with high-performance, leading-edge products.

Briefly described, the new process uses TEL wafer-prober technology in a controlled environment. It allows a batch of ICs on a silicon wafer to be electrically stressed across a range of temperatures up to 150?C. The prober, based on TEL`s Model P-8 and additional technology transferred from Matsushita Electric Industrial, automates the critical steps of the process, including contactor-to-wafer alignment, thermal control, signal interconnect, and power management.

The wafer being burned-in is held on a thermal chuck on the prober, while a contact head, with contacts for every die, is aligned to the wafer. Reliable contact is implemented via two GORE-developed (Eau Claire, WI) elements for the process: a full-wafer-barrier trademarked GoreMate and a thermally matched interconnect board trademarked Inferno.

 GoreMate is a z-axis (i.e., thickness direction) conductive, compliant film that carries electrical signals from probe contacts to the wafer. Its compliancy tolerates wafer surface variations.

 Inferno is an interconnect board (what would be called the probe card with conventional die-to-die probing) that matches the thermal expansion of the silicon wafer as it is heated and cooled. Inferno insures contactor-to-wafer positional tolerance.

Motorola expects to begin using this new manufacturing technology in 1999. Les Hazlett, wafer burn-in and test section manager at Motorola, explains, "We plan to apply this technology first to high-end chips, including fast static RAMS, PowerPC microprocessors, and embedded microcomputers. However, eventually nearly all chips are `fair game.`"- P.B.