Wafer-level packaging technology milestones

10/01/1998

Wafer-level packaging technology milestones

Texas Instruments (TI) has begun applying wafer level packaging with its storage product ICs, including wafers from Silicon Systems and Intersect Technologies. Specifically, TI is using Flip Chip Technologies` (FCT) proprietary solder wafer bumping technology and service (see "Chip scale and flip chip: Attractive solutions," SST, July 1998, p. 239). FCT is already bumping wafers containing TI Storage Products` preamplifier devices for hard disk drives, and other devices will be added in 4Q98.

As memory capacity and the data transfer rates of hard disk drives increase, signal-to-noise ratios become more critical. Traditional wire bonded solutions are giving way to low inductance, high speed interconnect using flip chip technology; its hard disk applications flip chip allows the pre-amplifier chip to be placed closer to the head assembly.

FCT received full qualification status with the TI Storage Products Group in mid-1998, based upon successful completion of all qualification plan requirements, including mechanical and physical integrity measurements, reliability stress tests, and FCT process control capability.

"FCT has demonstrated responsiveness in addressing our solder bump service needs," said Ron Yovan, senior staff quality assurance engineer for TI Storage Products. "We look forward to continuing to leverage FCT`s capabilities to provide HDD manufacturers the most advanced IC solutions available."

In a separate milestone, FCT`s new wafer-level technology, Ultra CSP, has achieved over 1000 hrs of thermal cycle testing with a 0.75-mm solder ball pitch, 6 ? 8 ball array test device, the current standard for flash memory. Thermal cycling ranged from -40?C to 125?C in one-hour cycles with 15 min dwells and ramps. The 0.75-mm pitch test vehicle was assembled to a FR4 test board with no underfill used. In addition, Ultra CSP has passed 1000 hrs of high temperature storage at 150?C, 1000 hrs of 85?C/85% relative humidity moisture contamination testing with a 5 V bias, and 1000 hrs of high temperature operating life at 125?C ambient (150?C junction temperature).

FCT is working with several flash memory manufacturers to qualify the Ultra CSP for use in cellular phone and other portable applications. The company expects the Ultra CSP to go into volume production in 4Q 1998, at which time FCT`s facility in Phoenix will have capacity of 4000 wafers/week.

At a price/lead of half of current chip scale package options and a price competitive with TSOPs (thin small outline packages), reportedly Ultra CSP is the most cost-effective chip scale packaging technology and reportedly offers superior inductance and capacitance performance over traditional wirebond packages and other CSPs. - P.B.