TI plans 0.1-um for 2001

10/01/1998

TI plans 0.1-?m for 2001

Texas Instruments (TI) has disclosed aggressive plans to bring a 0.1-?m patterned transistor mixed-signal CMOS process into volume production on 300-mm wafers by 2001. The production technology would enable effective transistor channel lengths of 0.07 ?m, and 1.2 V operation; up to 8 layers of all-copper interconnect are envisioned, as well as a yet-undetermined low-k dielectric material. TI`s plans will push all equipment and materials suppliers to the limits of rapid development, none more so than lithography vendors.

Senior technical staff member Peter Rickert said TI intends to use 193-nm exposure tools and photomasks featuring optical proximity correction (OPC) features, but not phase-shift technology, as it seeks a full-generation shrink below the previous 0.15-?m node.

"We expect to receive our first 193-nm tools in the middle of next year, and will start trying to tune the resists," said Rickert. "We will definitely use OPC; we`re applying it at the previous technology node, and it`s given a huge benefit. We`re trying to play with the resists and OPC to make sure we`ve gotten all the mileage we can - the infrastructure for phase-shift is not there, from the point of view of quality and cycle time. It`s slightly different in Japan, because of their emphasis on DRAMs. We`re trying to do things quickly; we went through a similar analysis at 0.15 ?m, and were able to get away without any phase shift. It`s more of an issue on contacts and vias, and you can play different games with OPC and anti-reflective coatings. We`re focusing on having a very good cycle time on lots of products."

Development of the process is under way now on 200-mm wafers at the Kilby research facility in Dallas, TX. Plans call for final designs to be initiated in 2000, with volume production beginning in 2001 at the planned DMOS-6 facility, which will be TI`s first 300-mm fab. Rickert noted that the fab shell is completed, and that TI "is in the equipment selection phase." TI hopes to receive its tools during 2000. "I don`t think we`ll see much in 1999," said Rickert.

Interconnect will use a dual-damascene process and all-copper metallization on seven or eight layers, with Metal 1 contact layers having a pitch of about 0.35 ?m, said Rickert. TI will begin using copper in production on high-performance devices next year in order to gain experience. A dielectric will be chosen from among "at least three" candidate materials, including TI`s xerogel material, added Rickert. "We will look at compatibility with copper, manufacturability, maturity, and electrical performance," he said. "We want a (dielectric constant) well below 3.0; in the 2.7 range."

A Ti barrier layer and TiN encapsulation layer will be used on the copper features, which Rickert indicated would be deposited using electrochemical deposition. Transistors will utilize shallow trench isolation with retrograde wells, and a sidewall on each side. Pocket implants will be used on "very shallow source-drain areas," noted Rickert. Achieving the necessary distortion and gain levels for analog operation at very low operating voltages poses a bigger challenge than isolation, he said.

The process will be used on a variety of devices, including DSPs, Sun UltraSPARC microprocessors, and system LSI mixed-signal chips. High-end chips will have a die size of about 150-200 mm2 , said Rickert, but the process will also be used on "cost-conscious chips" as small as 10 mm2. If TI is able to pull off the rapid transition to the new process, it will distort the outlines of the SIARoadmap planning document. The 1997 Roadmap does not envision 0.1-?m isolated lines for logic gates until 2003. - P.N.D.