Nine-inch reticles: An Analysis
10/01/1998
FIRST IN A SERIES
Nine-inch reticles: An analysis
Rajeev R. Singh, Sonny Vu, John R. Souza, Intel Corp., Santa Clara, California
One of today`s possible fundamental changes for semiconductor manufacturing is the adoption of so-called 9-in. reticles to replace 6-in. reticles. After they were officially defined in 1997 as 230 ? 230 ? 9 mm, the industry turned its attention to developing an infrastructure and defining standards for manufacturing 9-in. reticles. However, whether these larger reticles are adopted into production manufacturing or not is not just a question of availability, but rather requires a clear analysis of die-size trends and fab economics.
As the semiconductor industry enters the next millennium, there are a number of changes expected in manufacturing. The size of silicon wafers used for chip production will transition from 200 to 300 mm. Semiconductor lithography will shift from optical steppers to step-and-scan exposure tools with lower exposure wavelengths. Another possible change is the size of reticles used in optical lithography. We have analyzed the likelihood of this latter change.
Semiconductor industry lithography engineers began a debate on a new reticle size when the industry started looking at moving to 300-mm wafers. There was a need for improving productivity, and the potential of using a larger field size on new step-and-scan exposure tools coming into production offered such an opportunity. Also, there was a concern that future die sizes would outgrow the current 6-in. reticle size.
After a series of international meetings in the US and Japan, a consensus was reached in early 1997. The new reticle size was finalized at 230 ? 230 ? 9 mm - a "9-in. reticle." Since then, attention has focused on developing the infrastructure and defining standards for the manufacture of 9-in. reticles. However, decisions about introducing this new reticle size into manufacturing depend upon fab economics, unless die size is an overriding factor.
The die size question
Will the 6-in. reticle limit the ability of the industry to increase die sizes to meet the productivity improvement goals of Moore`s Law?
The 1997 National Technology Roadmap for Semiconductors ("the Roadmap") forecasts different requirements for future production critical-level lithography. Table 1 lists the relevant die size and field size requirements from the Roadmap [1] and compares them with available usable area on a 6-in. reticle.
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Field size requirements for future exposure systems are forecast to change from 22 ? 22 mm to 25 ? 32 mm at the 180-nm
technology node. Beyond that, field height is expected to remain at 25 mm, while the width increases every node. The available field size on a 6-in. reticle after 4:1 reduction is 35 ? 35 mm (i.e., 140 ? 140 mm on the reticle). Therefore, if field size requirements grow as predicted by the Roadmap, the 9-in. reticle would need to be inserted into production at the 130-nm technology node when the field-width requirement reaches 36 mm.
However, field-size requirements on the Roadmap are not as much of a driver as die-size requirements; the industry would not be compelled to change to 9-in. reticles as long as die-size growth is not being restricted.
The Roadmap shows die-size requirements for dynamic random access memory (DRAM) and microprocessor (MPU) chip generations with shrinks occurring each year after production for a given node starts. As volumes are not expected to be significant in the first year of production for any given DRAM or MPU, the cost of inserting a 9-in. reticle at that point will be difficult to justify; it is likely that semiconductor manufacturers will be inclined to deviate from the Roadmap and compromise on die size. However, it is expected that in the second year of production and beyond, there will be sufficient production volumes to justify a conversion from 6- to 9-in. reticles.
Using the DRAM die sizes in the second year of production as the indicator for change, the 9-in. reticle conversion would be needed at the 70-nm node when DRAM chip area reaches 900 mm2. This is because the largest usable field size on a 6-in. reticle is 25 ? 34 mm or 850 mm2. On the other hand, 6-in. reticles are not "limiters" for future MPU die-size growth.
Savings generated with 9-in. reticles
Use of 9-in. reticles will increase the number of dies exposed/field, enabling fewer steps to complete the exposure of a wafer. The resulting improvement in productivity can translate to cost savings realized from a reduction in the number of exposure tools needed to deliver the required output of a semiconductor factory.
The largest field size usable on a 6-in. 4?-reticle with currently planned exposure tools is 25 ? 32 mm. We compared the number of MPU die (assumed to be square) that can be exposed with this field size to that possible with the largest usable field size on a 9-in. reticle (i.e., 25 ? 50 mm); the results are listed in Table 2. It can be seen that the die/field (DPF) increase with a 9-in. reticle varies from 1.5? to 2?.
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The question arises: What is the increase in productivity that can be realized from the increase in DPF?
We considered the step-and-scan exposure tool for which throughput depends on the number of fields to expose, scan rate, step-and-align time, wafer change time, and other overhead time. An analysis at Intel, based on an internal presentation and using proprietary numbers for the above parameters, showed that the exposure tool run-rate gains that can be achieved with a 9-in. reticle are in the order of:
10-15% when there is a 1.5? DPF increase, and
20-30% when there is a 2? DPF increase.
We calculated the savings generated from these improvements in run rate using the following assumptions:
1. The exposure tools required would be for
a 300-mm factory with 5000 wafer starts/week, and
a process with 20 layers using a mix of 193-, 248-, and 365-nm lithography systems, with
system utilization varying from 70-85%.
2. The cost difference between a 6-in.-reticle-capable and 9-in.-reticle-capable exposure system would be in the order of $100,000 (Case 1) and $500,000 (Case 2). (These values are speculative, but our purpose was to develop a sensitivity analysis.)
3. Net reduction in cleanroom costs
was on the order of 0.1% of 300-mm wafer cost, due to
reduced floor space requirements for fewer exposure systems, and
increased floor space requirements for 9-in. reticle stockers.
We calculated savings in wafer cost using the above assumptions for a range of run-rate improvements from 15-30%. The results of these calculations (Fig. 1) show that savings range from 1.6% to 3.2% of the wafer cost. There was no difference in the savings for the 15-20% improvement range because the number of tools required were the same due to rounding to whole numbers.
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Figure 1. Productivity improvement savings when using 9-in. reticles.
Cost contribution of 9-in. reticles
The contributing factors we used for determining the cost of a 9-in. reticle include
capital investment,
development costs,
raw materials, labor, and processing costs, and
cost allocation based on total mask demand, which is driven by mask utilization (i.e., wafers exposed/mask) and total wafer demand.
We obtained data on the utilization of reticles from two industry sources that agreed closely (Table 3).
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The average number for wafers
eticle is fairly low, which we believe can be attributed to the frequency of product changes and the number of redesigns in a product life cycle.
In our analysis, we used 4500, 7000, and 9000 wafers/mask. This range of mask utilization represents cases more favorable to 9-in. reticle economics and were chosen based on internal considerations. We used a wide range of wafer start levels to determine 9-in. reticle demand: 2000, 8000, and 24,000 wafer starts/week.
We analyzed the impact of direct costs by using only the incremental cost of making 9-in. reticles compared to 6 in. In determining this extra cost we assumed:
Write area would increase 2? and would proportionally increase capacity needs for mask writing, inspection, and repair tools.
At the time of 9-in. conversion (i.e., at the 130-nm node or beyond), most maskmaking tools in use or being newly purchased would most likely be both 6- and 9-in. compatible. Therefore, to determine the incremental cost, we only considered those current tools (e.g., inspection microscopes, pellicle mounters, etc.) that we believed would continue to be used until the 130-nm node and could therefore be reused if 9-in. conversion did not occur.
9-in. reticle blank cost would increase 4? because of the weight increase of quartz.
Yield on 9-in. reticles would be 10% lower than that for 6 in.
In Fig. 2 and Table 4, we show the results of calculations made for a mask usage case of 7000 wafers/mask. The three graphs plotted are for reticle demand (Fig. 2a), incremental 9-in. reticle cost as a ratio of 6-in. reticle cost (Fig. 2b), and percentage cost/wafer increase for 9-in. reticle usage (Fig. 2c). These results show that as reticle demand increases from 800 to 6500, the cost premium for a 9-in. reticle versus a 6-in. reticle, as a ratio of 6-in. reticle cost, decreases from 2.2? to 0.9?. In terms of wafer cost, the contribution from the 9-in. reticle changes from 6.25% to 2.5%.
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Figure 2. For 7000 wafers/mask, a) 9-in. reticle demand, b) incremental 9-in. reticle cost as a ratio of 6-in. reticle cost, and c) wafer cost increase due to incremental 9-in. reticle cost, all plotted per 300-mm wafer starts/week.
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Cost vs. savings comparison
All cases considered in this analysis, for both savings and cost, have been plotted together in Fig. 3. The horizontal lines on this plot represent the different savings cases considered (i.e., three cases of savings at run rate gain). The point where a 9-in. reticle becomes cost effective is where a cost line goes below the savings line.
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Figure 3. Cost/wafer impact of 9-in. reticles. Horizontal lines represent four different savings scenarios: a) 25% run-rate improvement, $100,000 exposure tool cost increase, b) 25% run-rate improvement, $500,000 tool increase, c)15-20% run-rate improvement, $100,000 tool increase, d) 15-20% run-rate improvement, $500,000 tool increase. Sloped lines represent three different cost scenarios at 1) 4500, 2) 7000, and 3) 9000 wafers
eticle. (In other words, horizontal lines equal savings at run rate gain, and sloped lines equal cost at wafers/mask.) Nine-in. reticles become cost effective in a particular scenario when a sloping line drops below a horizontal line.
Consider the horizontal line for a run rate improvement of 25% and an exposure tool cost difference of $100,000. This provides a savings of 3% in terms of wafer cost. The sloped line for mask cost at 4500 wafers/mask crosses this line at about 14,000 wafer starts/week. The mask demand at this level can be calculated. If mask utilization increases to 7000 wafers/mask, the mask demand required to break even will correspond to 12,000 wafer starts/week. As long as the cost implications for a particular case fall below the savings line, the use of 9-in. reticles can be economically justified.
Such conditions can be expected if:
High wafer volumes are supported so that capital and development costs of 9-in. reticles are spread out over a larger reticle volume.
Mask utilization (i.e., the number of wafers/mask) is high.
High productivity improvements are accomplished on exposure tools, while the cost difference between 6- and 9-in. reticle-capable tools is kept low.
Conclusion
In this analysis, we have shown that the primary driver for the semiconductor industry to insert 9-in. reticles into manufacturing will be fab economics. With respect to die size, there are no real show stoppers until after the 100-nm technology node. Therefore, unless a die size limit is reached, conversion to the next reticle size of 9-in. will only happen if the increase in cost can be offset by savings realized from productivity improvements.
The conclusion reached in this analysis is based on forecasts made in the National Technology Roadmap for Semiconductors and assumptions used for 9-in. reticle costs and exposure tool costs and capabilities. As the industry moves forward, and more accurate information becomes available, we recommend revisiting this analysis.
Acknowledgments
The authors acknowledge the contributions to this analysis by M. Goldstein, P. Silverman, M. Dinda, J. Golda, and P. Gargini.
References
1. Table 24 in The National Technology Roadmap for Semiconductors, Semiconductor Industry Association, 1997.
2. K. Early, W. H. Arnold, "Cost of Ownership for X-Ray Proximity Lithography," Proceedings SPIE Vol. 2194, pp. 22-33, 1994.
3. R.J. Smith, Etec Systems Inc., verbal communication, Feb. 1998.
RAJEEV SINGH received his BS and MS in chemical engineering from Indian Institute of Technology, Kanpur, India, and University of Akron, OH. Singh has worked at Intel for 10 years and is currently manager of a reticles and metrology group. Intel Corp., SC2-16, 2200 Mission College Blvd., Santa Clara, CA 95052; ph 408/765-0089, fax 408/765-2554, email [email protected].
SONNY VU received his BSfrom Texas A&M University, College Station, and his MBA from University of Texas, Austin. He worked in Intel`s finance department from 1996 to 1998. He is currently a financial analyst at Exxon in Houston, TX.
JOHN SOUZA received his MBA and MS in chemical engineering from the Massachusetts Institute of Technology. Souza is working on Intel`s 300-mm wafer program.