Low-temperature pre-metal dielectrics for future Ics
09/01/1998
COVER ARTICLE
Low-temperature pre-metal dielectrics for future ICs
Somnath Nag, Raman Ramamurthy, W. Jack Lei, Christophe Monteil, Mark Hickey, Watkins-Johnson Co., Scotts Valley, California
Reduced thermal budgets for pre-metal dielectric deposition mandate a change to plasma-based chemical vapor deposition processes. A high-density-plasma-CVD phosphosilicate glass process is an attractive solution due to its lower deposition temperature and good gap-fill. Electrical tests show the plasma process does not degrade device performance.
The pre-metal dielectric (PMD) layer isolates transistors in an IC in two important ways. It isolates them electrically from the metal interconnect layers, and it isolates them physically from contamination sources such as mobile ions (from post-processing and handling). Mobile ions such as Na+ and K+ degrade essential device characteristics such as the threshold voltage (VT) of a transistor.
Borophosphosilicate glass (BPSG) - SiO2 containing about 2-6 wt% each of boron and phosphorus - has traditionally been used as the PMD (Fig. 1). BPSG is usually deposited using thermal chemical vapor deposition (CVD) at 500-700?C, and then annealed at 800-1000?C. The phosphorus in BPSG acts as the gettering agent for any mobile ions that may diffuse toward the transistors, while the boron "softens" the layer to ensure sufficient planarity after the reflow anneal.
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Figure 1. The pre-metal dielectric layer isolates active devices from the electrical signals in metal interconnects and from ionic contamination.
PMD layers are deposited using a variety of technologies, depending on device type. Memory applications typically use atmospheric pressure CVD (APCVD) due to available high-productivity systems and the flexibility to perform reflow at high temperature. High-performance logic, on the other hand, has restricted thermal budgets for PMD in order to preserve transistor characteristics.
In addition to producing a film with acceptable barrier properties, the PMD layer must have a relatively planar final top surface, with void-free gap-fill of the spaces between polysilicon lines. The film must also maintain stability against moisture and thermal stress induced by post-processing. These requirements are harder to meet as devices move into the sub-0.25-?m regime due to tightened specs on DOF, planarity, thermal budget, and gap-fill (Table 1).
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Though chemical mechanical polishing (CMP) will still be required to ensure optimal planarity of the PMD layer, improved as-deposited planarity minimizes both deposition and CMP process times. The DOF is directly proportional to the size of the feature to be printed and is there fore tighter for advanced technologies. For instance, the DOF budget allowable at PMD for the 0.18-?m node is only 0.7?m [1].
In addition to the tightening planarity specs, thermal budgets are rapidly dropping. The sub-0.25-?m generations need lower-temperature processing to maintain low silicide sheet resistance, low contact resistance, and the shallow junctions that are critical for device performance. For example, titanium and cobalt silicides (first anticipated at 0.18 ?m) undergo phase transformations at around 600?C that increase their contact resistance [2] to unacceptable levels.
Low processing temperatures facilitate high transistor drive currents by preventing degradation in key gate oxide parameters such as Cinv/Cox, and reducing dopant deactivation [3]. Low temperatures also limit boron diffusion from the gate polysilicon to the channel area, minimizing change of transistor VT. Larger wafers also necessitate lower processing temperatures, since the thermally driven risk of warpage and breakage increases with wafer size.
The spaces between polysilicon lines can be as small as 0.1 ?m for logic and memory applications at the 0.18-?m node, with aspect ratios (AR) as high as 5:1. However, it is difficult for conventional PMD processes to meet the simultaneous requirements for 0.1-?m gap-filling with a low thermal budget.
The low-thermal-budget requirement points toward plasma processes as future PMD solutions. Plasma CVD processes typically do not require a high-temperature reflow because of their superior gap-fill capability, so the B-doping can be eliminated from the process. Processes for plasma-enhanced CVD (PECVD) of phosphosilicate glass (PSG) and BPSG have recently been developed to replace thermal techniques. Recent work also suggests that advanced anneals can aid APCVD process solutions.
Although capacitively coupled plasma processes may have reasonable gap-fill capability down to 0.5 ?m with sloped walls, a high-temperature anneal may still be required to stabilize the material. High-density-plasma-CVD (HDP-CVD)-based processes, however, have superior gap-filling capability [4, 5] and produce stable films as deposited. A phosphine (PH3)-based chemistry was used in a HDP reactor to deposit PSG films for PMD and passivation applications.
Process development
A WJ-2000/3000H HDP-CVD process chamber deposited the PSG films used in this study. Process parameters used to control film properties included plasma-source RF power, bias RF power, gas flows (SiH4, PH3, O2, Ar), process pressure, electrostatic clamping (ESC) voltage, and helium pressure at the wafer backside. Wafer temperature was controlled by adjusting the bias RF power, ESC voltage, and backside helium pressure.
PH3 was the precursor gas for the phosphorus. As with the HDP-CVD undoped silicate glass (USG) process, the PSG deposition rate increased with increasing SiH4 flow and decreased with increasing bias RF power. The PSG process temperature varied from 250-550?C. After optimization, all film targets were met (Table 2).
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The wt% of P in the PSG film monotonically increases with declining deposition temperature and increasing PH3 in the gas mixture (Fig. 2). P uniformity is critical for many film properties, particularly the gettering that is essential to final device performance. The across-wafer wt% P uniformity is a function of two parameters that influence surface reactions: precursor delivery to the growth surface (dependent on gas distribution and plasma uniformity), and the temperature uniformity across the wafer surface (balancing frontside ion bombardment and backside cooling).
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Figure 2. The amount of phosphorous incorporated into the final film is directly proportional to the flow of precursor gas into the deposition chamber.
Film stability
For complete process integration, PSG films must be stable when exposed to both moisture and thermal stress. Stability of the PSG films was evaluated using three different test conditions: ambient exposure (10 days), thermal cycling (3? 450?C, 30 min, N2), and steam treatment (120?C, 1 hr, 2 atmospheres). Fourier transform infrared (FTIR) spectra, wt% P by x-ray photoelectron spectroscopy, film thickness shrinkage, and stress were monitored to measure any changes resulting from these stability tests.
Fourier transform infrared spectra show qualitative and quantitative measures of oxide bonding (particularly the phosphorous-to-oxygen double bond denoted P=0, and the silicon-to-oxygen double bond denoted Si=O) and moisture content. FTIR peaks at 1330 cm-1 (for P=O) and 3600 cm-1 (for moisture species) were monitored for changes pre- and post-exposure. Moisture pickup can also be seen as change in film stress. Changes in the film density were detected by variation in the refractive index. The ratios of the areas under the P=O and Si=O peaks did not change after the 450?C anneal cycles.
A strong correlation was found between PSG film stability and both the wt% P and the deposition temperature. Generally, HDP-CVD PSG films deposited at higher temperatures had a lower wt% P and were more stable to moisture and thermal treatments. It is not clear if the stability was a stronger function of deposition temperature or of the wt% P in the final film.
Optimized PSG films deposited with this process showed a P=O peak at 1330 cm-1 in the FTIR scan. Phosphorous can be incorporated into glasses as either stable P2O5 or unstable P2O3. The relative amounts of each can be determined by measuring a film with both inductively coupled plasma atomic emission spectroscopy (ICP-AES) and colorimetry. ICP-AES measures the total wt% P (P2O5 + P2O3), while colorimetry measures P2O5 only; comparison of the two indicated that all the P in these films was in the stable P2O5 form.
Although the wt% P for the low-temperature deposited film does not vary with either thermal or moisture treatments, the full-width half maximum of the P=O peak in the FTIR spectrum shrank after the 3? 450?C thermal cycles. The P=O peak also significantly deconvoluted from the Si=O peak following the anneals (Fig. 3), indicating that the P=O bonds had a tighter distribution of stable bond lengths, angles, and strengths [6]. The metallization cycles that occur after PMD deposition may make the film more stable.
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Figure 3. Though the wt% P is stable for anticipated temperature and moisture exposures, the P=O peak in the FTIR spectrum is narrower and significantly deconvoluted from the Si=O peak after 3? 450?C anneals; a) before and b) after anneals.
Gas handling and safety issues
P incorporation efficiency for the HDP-CVD PSG process is typically around 25%. Therefore, to deposit PSG films with 6-10 wt% P, it becomes necessary to use gas mixtures with 30-50% PH3 in a diluent. However, PH3 gas in this concentration range may be a safety concern in wafer fabs. Various diluent gases such as N2, Ar, He, H2, and SiH4 have been proposed to balance process efficiency and safety.
He and SiH4 seem to alter the film deposition process the least. N2 can cause incorporation of silicon nitride in the PSG. Ar causes uncontrolled ion bombardment on the growth surface, which limits the amount of P that can be incorporated in the film. Moreover, excessive amounts of Ar (for example, 10% PH3/90% Ar) may limit the deposition rate and the throughput of the PSG process.
To attain target wt% P with very low PH3 dilution requires extremely high precursor gas flow, which increases process chamber pressure. However, the simultaneous sputtering during deposition of HDP-CVD (required for tight gap-fill) becomes ineffective at pressures above approximately 10-20 mT. Although the concentration of PH3 in the gas phase that will be permitted by fab safety is still uncertain, significantly high ratios will be required for a HDP-CVD PSG process with acceptable throughput for manufacturing.
Recently, alternate sources have been investigated for the delivery of required PH3 flows to the HDP-CVD chamber without compromising the safety of fab personnel. One of these is a solid source onto which PH3 is adsorbed and stored; sub-atmospheric pressures draw pure PH3 from the solid surface. While this source has many desirable characteristics, technical details such as maximum flows and manufacturability have yet to be tested.
Gap-fill and planarization
Gap-fill is achieved by controlling gas flows and the bias RF power component (that accelerates bombarding ions toward the wafer). Increasing the ion bombardment increases the etch component of the etch-deposition (E/D) characteristic. Gap-fill was achieved in multiple steps by varying the E/D ratio during process to avoid both corner clipping (at the tops of gaps) and the sidewall build-up that tends to create voids [7].
Due to simultaneous deposition and sputtering [4], the HDP-CVD PSG process resulted in good local planarity over polysilicon line/space arrays. This self-planarization effect was greater for the PSG process as compared to HDP-CVD of undoped oxide.
As deposited planarity of HDP-CVD PSG can significantly reduce the CMP process time required after PMD deposition. The self-planarization eliminates the need for reflow. The self-planarizing characteristic of the process and the as deposited film stability are the primary reasons that HDP-CVD PSG can be a low-thermal-budget
PMD process. Excellent results were obtained in filling a typical PMD structure with 0.063-?m spaces between lines of polysilicon with nitride sidewall spacers (Fig. 4).
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Figure 4. Scanning electron microscope (SEM) image of HDP-CVD PSG gap-fill of 0.063-?m spaces between nitride sidewalls, showing the extendibility of the process.
Good as deposited local planarity of HDP-CVD PSG is achieved compared to PECVD PSG, post-reflow BPSG, or HDP-CVD USG. Therefore, the net amount of oxide that must be removed during CMP to achieve similar planarity should be much lower for HDP-CVD PSG. With a thinner as deposited PMD film and a shorter CMP process time, the overall PMD process time can be reduced with a corresponding drop in cost. This same process fills 4.5:1 AR 0.18-?m gaps in a typical PMD structure for DRAMs (Fig. 5).
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Figure 5. SEM of HDP-CVD PSG filling 4.5:1 AR 0.18-?m gaps in a typical PMD structure for DRAMs, showing that minimal topside deposition allows for a reduction in the post-deposition CMP processing time.
Electrical measurements
A common concern with plasma processes is the electrical damage to on-chip devices that may result from the charges in the plasma. Damage has been associated with plasma nonuniformity at the wafer surface or transients during wafer processing [8]. In particular, there is reluctance to use HDP-based processes close to transistors, such as at the PMD level.
We used SPIDER antenna structures from SEMATECH (with antenna ratios up to 90,000) as test vehicles to evaluate charge damage. The antennae were at the level of Metal 1, and connected by W-plugs to the polysilicon gates of the transistors. Conventional thermal PMD isolated the polysilicon from Metal 1. The test transistors had 0.35-?m gate lengths and 45-? gate oxide thickness.
After HDP-CVD PSG was deposited over the Metal 1 antennae, changes in VT and gate leakage current (Ig) were monitored to study any charge damage post-deposition and after constant current Fowler-Nordheim stress. Both tests showed that VT shift and Ig were well below the levels considered problematic to device performance. A slight antenna dependence seen for Ig and outliers was attributed to a plasma process used to fabricate the test structures themselves.
The PMD layer is typically separated from the transistor polysilicon by a thin layer (1000-2000 ?) of undoped oxide. Since the PMD is quite close to the transistor, any charges in the PMD oxide can degrade transistor parameters such as VT. We measured C-V on MOS capacitor structures to determine fixed oxide charge for HDP-CVD USG (as used for shallow trench isolation) and PSG films. Since the fixed charge densities were both in the 5?1011/cm2 range, and since the USG process is proven in shallow trench isolation (with more stringent fixed charge specs), the HDP-CVD PSG process should not create charging problems at the PMD level.
Conclusion
Requirements for the PMD layer for high-performance logic are being reassessed at the 0.18-?m technology node, primarily due to the need for a low thermal budget. Traditional thermal BPSG processes may not satisfy all the stringent PMD specifications simultaneously. A HDP-CVD PSG process offers an attractive drop-in solution for sub-0.25-?m PMD, and can improve final device performance and reduce the cost-of-ownership.
Acknowledgment
The authors are grateful for the technical assistance provided by J. Casillas and M. McManus during process development. Also, helpful discussions with J. Werking, M. Shapiro, K. Taylor, A. Chatterjee, J. Bondur, and R. Savage are greatly appreciated.
References
1. K. Brown, Tech. Roadmap for Semiconductors, p. 21, SEMI Tech. Symp. 1997, SEMICON Japan, Dec. 3-5, 1997.
2. K. Maex, Materials Science and Engineering Reports: A Review Journal, Vol. R16, No. 2, p. 129, Feb. 1996.
3. J. Bevk et al., IEDM Tech. Digest, p. 893, 1995.
4. S. Nag et al., Proc. VMIC, p. 24, 1995.
5. S. Nag et al., IEDM Tech. Digest, p. 585, 1996.
6. J. Franke et al., Spectrochimica Acta, Vol. 50A, No. 10, p.1687, 1994.
7. J. Li, doctoral dissertation, Stanford Univ., p. 285, Mar. 1996.
8. S. Fang, J. McVittie, J. App. Phys., Vol. 72, p. 4685, 1992.
SOMNATH NAG received a PhD in solid state science, MS in materials science, and BTech in metallurgical engineering. He joined Watkins-Johnson in 1997, where he is manager of process development, involved in R&D in plasma technology. Watkins-Johnson Co., 440 Kings Village Rd., Scotts Valley, CA 95066; ph 408/439-4863, fax 408/439-8993.
RAMAN RAMAMURTHY received his BS in chemical engineering from Osmania University in India, and his MS in chemical engineering from Oklahoma State University. He is a process engineer with Watkins-Johnson`s high-density plasma R&D group.
W. JACK LEI received his PhD degree in materials science and engineering from the University of Illinois, Urbana-Champaign, in 1995. He is a technical staff member in the customer applications engineering department at Watkins-Johnson, where he serves East Coast customers.
CHRISTOPHE MONTEIL received his PhD in 1993 from the University of Montpellier, France. He is a senior process engineer for dielectrics at Watkins-Johnson.
MARK HICKEY received his BS in chemical engineering from the University of California, Santa Barbara, in 1993. He has worked as a process engineer in the customer applications group at Watkins-Johnson since 1996.