Rapid innovation in spite of slow market
09/01/1998
Rapid innovation in spite of slow market
A special report by the Solid State Technology and WaferNews editorial staffs
In a technology-driven business such as chipmaking, the spirits of invention and innovation are always present, even when markets are soft, and this year`s show featured many examples. Indeed, a number of attendees pointed out that downturns are an ideal time for bringing new technology into play because chipmakers are looking for fresh ideas.
300-mm news
Perhaps the most important advanced technology news at the show was the disclosure that the International 300-mm Initiative (I300I) will open a new avenue for 300-mm development by offering one-on-one equipment improvement programs with process tool companies. I300I officials and representatives from member companies held closed-door meetings during the show to discuss toolmakers` growing concerns over the slow transition to 300-mm wafer usage and the lack of return on investments in 300-mm tool development.
SEMATECH president/CEO Mark Melliar-Smith acknowledged that chip demand growth has been slower than expected, while 200-mm productivity improvement has been faster. "There`s not a compelling reason to change (to 300 mm), and that changes the business dynamics for the suppliers," he said. "We recognize that, and will meet to help them. We live or die together as an industry. We`ve had requests from suppliers to go back to see if there are cheaper ways of doing things, and we will do that." Toolmakers also want increased dialogue and a better understanding of 300-mm economics, he said.
Melliar-Smith said I300I tool demos will be finished by mid-1999. Around the beginning of that year, one-on-one equipment improvement programs will begin, focusing on throughput, MTBF, cleanliness, and other issues. "We will provide funding, and an individual for each tool to ensure that we`re inextricably linked," said Melliar-Smith. Most work will be done at supplier locations, with administration through SEMATECH`s technical thrust areas rather than I300I.
Lithography
Canon introduced a new DUV step-and-scan exposure tool with 300-mm wafer capability. The new FPA-5000ES2 will have a 0.68 NA lens, capable of patterning 26 ? 33-mm fields with 0.18-?m circuits. Using 200-mm wafers, the nominal throughput is 100 wafers/hr.
SVG Lithography also announced a new step-and-scan exposure tool, the Micrascan III+. With a 26 ? 34-mm field and a 0.68 NA lens, this tool offers the largest field for 0.18-?m critical layers. The nominal throughput is 90, 200-mm wafers/hr. Shipments are expected in late 1998. SVGL also anticipates first shipments of a new 193-nm exposure tool in the first half of 1999. Since the catadioptric design of the Micrascan tolerates larger laser linewidths and requires only three small CaF2 elements, this new tool should produce 25 wafers/hr using an available 15-W excimer laser and a resist with 20 mJ/cm sensitivity, according to John Shamaly, corporate VP of marketing at SVGL.
ASM Lithography expects to deliver its first full-field 193-nm exposure tool to IMEC in Leuven, Belgium, in January 1999. The lens has already been delivered to ASML by Zeiss. According to Luc van den Hove, head of micropatterning at IMEC, that scanner will be incorporated into the IMEC 193-nm lithography program, which will research CD control and across-chip linewidth variation. Over the next three years, that program is expected to grow to 40 people representing 25 industrial partners.
Rather than announcing new exposure platforms, Nikon focused on incremental improvements. The NikonNest controller for 5- to 10-series steppers has been upgraded to run on Windows NT. Power-Up illumination enhancements improve throughput on 6- through 10-series steppers. Two new optimization reticles, one for focus and one for alignment, decrease set-up time.
The plan to shrink CDs to 0.18 ?m and below requires improvements in photomask writing, and ETEC announced a new product, the MEBES 5000 electron beam mask writer, for 0.18-?m development and pilot line applications. Available in the first half of 1999, the MEBES 5000 boasts a 360-nm minimum feature size and a 35-nm composite CD uniformity, with 30-nm placement and overlay accuracy. With twin data channels operating at 160 MHz, the new machine claims twice the throughput of the MEBES 4500S, on new ZEP 7000 resist. The new Mode 5 MEBES data format reduces file sizes by a factor of 4 and supports grid spacings down to 1 nm, although the minimum grid on the 5000 will be 10 nm.
While the MEBES 5000 is clearly a step forward, complicated 0.18-?m-generation masks will still take more than 4 hrs to write. Something much faster is needed for production applications, scheduled for 1999-2000. Wally Carpenter of SEMATECH summarized the industry reaction, "Let`s hope there is another tool next year."
The issue of photomask cost evoked considerable concern at the presentations and in the aisles. Gerhard Gross, the new director of lithography at International SEMATECH, predicted photomask costs of $100,000 each for the 0.13-?m generation, too much for the ASIC segment (see figure on p. 42). However, he held up the hope that post-optical lithography mask costs would be less. Van den Hove of IMEC noted that a multibeam mask writer was the tool really needed. John A. Doherty, VP of marketing of Micrion, warned that mask repair was falling further and further behind due to the lack of investment, "The whole mask repair equipment business over the next 10 years is only $100M."
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Mask cost trends.
Arthur Zafiropoulo, president of Ultratech Stepper, is betting that photomasks will become critical in the next 12-18 months, but that the industry will earn enough to buy numerous Ultrabeam mask writers. "Maskmakers are not gouging, even at $1 million/mask set," claimed Zafiropoulo. In further analysis of the current situation, Zafiropoulo explained that a new technology must be able to print 100 million in.2 of silicon/year to make an impact in semiconductor production. Getting to that level requires an industry sponsor capable of investing $250 million. X-ray, EUV, and SCALPEL have such sponsors.
Materials
The new MEMS-based mass flow controller (MFC) from Redwoods Microelectronics represents a breakthrough in micromachine applications (see figure). The MEMS-Flow MFC uses a proportional microvalve compatible with most process gases and liquids, pressure and temperature sensors, and a calibrated orifice.
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The new MEMS-based mass flow controller from Redwoods Microelectronics.
The small footprint of the MFC module (38 ? 38 ? 10 mm) allows mounting on standard stainless steel manifolds with VCR fittings. Combined with electronics, it provides convenient plug-and-play replacement for conventional MFCs in a configuration that measures 39 ? 39 ? 57 mm. The pressure-based flow sensing technology can control flow rates between 0.2 and 2000 sccm with high levels of accuracy (?1% of reading), repeatability (?0.2% of reading), and resolution (0.25% of reading). Since the valve has no moving mechanical parts, there is reduced particle generation during gas regulation. The smaller interval volumes also leave less surface area for moisture absorption.
Most show attendees didn`t notice the unobtrusive 400-mm wafers on display at the TSK America booths in both Moscone and San Jose. Crystal weight would be four times the 100 kg of today`s 200-mm wafers, with flatness <0.13 ?m vs 0.35 ?m with today`s 200-mm wafers, with metal impurities under 108 atoms/cm2 vs 1010 today. The purity target for the wafer crystals is equivalent to 1 mg of sugar dissolved in an Olympic-sized swimming pool. Development work is being done by the Super Silicon Crystal Research Institute, Nakanoya, Japan.
BF Goodrich`s Corzan 4910 comes right down on fire hazards, which can cripple production. Corzan 4910 is a CPVC material that meets Factory Mutual requirements on flame propagation, smoke development, and corrosion resistance for the semiconductor industry. Meeting all system strength weldability and chemical resistance requirements, this material is touted as a cost-effective alternative to the conventional, but less safe plastics used for wet chemistry systems (i.e., ECTFE, PTFE, and PVDF). Released for OEM application in July 1998, SEMICON exhibitors already showing Corzan products included emission control engineers KCH Services, wet chemistry parts cleaner manufacturer Poly Flow Engineering, industrial distributor Peninsula Valve/Compression Polymers, and scrubber manufacturer Gradient Point.
Deposition/etch/CMP
Much of the industry was eager to discuss the newest processes for sale to produce copper dual-damascene interconnects. It`s certain that copper will be used, but the timing and details of implementation are still unclear. Novellus unveiled its new electrochemical deposition (ECD) tool, with help from processing partner (and leader in copper interconnect technology) IBM; Lam Research and IPEC are also partners in the Damascus plan. Semitool showed a redesigned ECD tool, the LT-210c, with smaller footprint, increased throughput, and a new clamping mechanism (comparable to Novellus`) that effectively isolates a wafer`s backside and edge from the plating bath. Novellus also showed, in an invitation-only back room, its Parylene-AF4 low-k (2.5) dielectric deposition tool. The Parylene reaction is significantly different from all other low-k processes: solid source material is sublimated, the vapor is pre-reacted in an elevated temperature chamber, and the final vapor deposits on the wafer surface. Wilbert van den Hoek, leader of Novellus` Parylene effort, stated that the proper temperature in the pre-reaction chamber allows the system to achieve deposition rates over 2000 ?/min.
Applied Materials unveiled a small but significant technology for cleaning exposed copper at the bottom of a via without redepositing the copper on sidewalls. Prior to the deposition of the barrier/seed layers in the via (for damascene processing), the exposed surface of the lower copper line must be cleaned to ensure good electrical contact. Applied Materials` innovation is a "reactive pre-clean" that used a low-energy hydrogen plasma to reduce the native copper oxide surface to pure metallic copper. The only byproduct of the reaction is water vapor. The reactive pre-clean module is available on the company`s Endura PVD platform.
AG Associates introduced STEAMpulse, a new RTP system capable of both catalytic and pyrogenic steam generation for the production of oxide films. Steam technology opens up a number of new process applications for RTP, including thin gate/capacitor oxide, thick STI liner oxide, BPSG reflow, and selective gate oxidation. Differing from competitive RTP steam-based systems, STEAMpulse creates its steam concentration (up to 40%) outside the processing chamber rather than inside.
Chartered Semiconductor`s CMP program is seeing rapid growth as it brings up 0.35-?m and below processes, but the Singapore foundry is finding that a lack of local consumables support has become a critical issue in implementing the CMP process throughout its fabs. Speaking at the SEMI-sponsored CMP Technology for ULSI Interconnection symposium at SEMICON West, Jiazhen Zheng, Chartered`s section manager for R&D/CMP, said supplier support in Singapore for its CMP process is "a parameter as important as the performance and (cost of ownership)."
US Filter, backed by its relatively healthy business units outside of the semiconductor industry, has taken advantage of the industry downturn to acquire companies and establish itself in the semiconductor equipment market. Its recent acquisitions include Memtec, Kinetics Group, Mega Systems and Chemicals, and Unit Instruments. Combining the company`s reverse osmosis wastewater treatment
ecycle technology and membrane filters with Memtec`s CMP filtration experience, US Filter introduced its new copper CMP recovery system and CMP multitool wastewater reclamation system. The recovery system removes copper from the CMP slurry, discharging copper-free water to the sub-fab drain while the reclamation system processes the wastewater streams through crossflow membrane microfilters. Since the wastewater contains higher levels of contaminants, reverse osmosis together with proper treatment provides purification of the reclaimed wastewater. Test results will be available from SEMATECH this fall.
CMP tool supplier Strasbaugh showed a productivity enhancement, developed with control software company MiTeX Solutions, Canton, MI. The new automated process control (APC) solution uses the data from in-line NovaScan sensors to achieve closed-loop, run-to-run control. Since CMP consumables (particularly pads) continuously change during processing, the concept of process control needs to be re-examined. Instead of controlling process around an unmoving center line (such as processing time), this new approach recognizes that the optimum conditions to achieve endpoint continuously change over one consumable-set`s lifetime. Thus, optimal control can be thought of as centered around a subtly complex curve (instead of a simple flat line) that can only be followed with in-line feedback.
Automation/fab management
Converging factors seem to be driving OEMs to seek their wafer handling automation solutions from collaborating suppliers. Automation Modules (AMI) president Sudhir Jain noted, "The typical process tool development cycle for a new generation of semiconductor equipment runs 18 months or more." Engaging a materials handling supplier for a new tool can remove up to a third of that time from the OEM`s development plate.
The other factor is the breadth of future applications for automated wafer handling, especially for 300-mm fabs. Charles Janac, president of Smart Machines, stated, "The number of robots needed for process tool automation in a $2 billion plus 300-mm wafer fab will be enormous. This need is growing dramatically from even impressive numbers in a 200-mm $1 billion fab where, for example, we see upwards of 120 vacuum robots in process tools." The majority of semiconductor process tool manufacturers require two to three front opening unified pods or three to four integrated standard mechanical interface pods in front of their tools. These all require robotic handling.
Dan McNerney of LANs End Development Corp., a software firm in San Francisco, says he is working with IBM on a project to link all the steps in the processes in a fab at IBM. The goal is to coordinate process flow. If an etcher has a cassette waiting, for example, and another one is in an oven being readied for etch, it would be held in the oven until the etcher was available so that the wafers would not cool down before processing. Universal serial bus (USB) links would tie all tools to a computer network, and computers at each tool station would be directed by a central computer. McNerney says two identical process lines in Fishkill will be set up, one with the USB connections, the other without them, and the results compared. He claims that misprocessing occurs every day in fabs, and that this approach could potentially eliminate over 90% of it. The software entrepreneur says he worked for several years at IBM in fab operations. He is discussing a similar arrangement with Electroglas for back-end processing, using the software developed in collaboration with IBM.
With nearly all world chipmakers reporting budget cuts, there is renewed interest in alternatives to simple purchase orders. CVC and Venlease Associates announced the formation of "CVC Financial Advantage," that will offer customers "wafer scale pricing" that converts fixed equipment cost into a variable cost based on the number of good throughput wafers. TEFEN, the industrial engineering firm, announced that its spare parts inventory, cost of ownership, and reticle management software packages are now offered with "success-based" pricing that rewards TEFEN with a percentage of cost reduction realized by its customers.
Packaging/back-end
Evidence of intensive technology development for ball-grid array, chip scale, and flip chip packaging was everywhere in the San Jose exhibits. One example: Thermaxx adhesive for attaching the heat-sink to a flip-chip package introduced by Ablestik, Rancho Dominguez, CA. Offering 7-10 times the heat conductivity of conventional adhesives, Thermaxx consists of 80-90% conductive fillers (silver) with 10% solvent and only 10% polymer resin. After curing, tightly packed silver particles offer superior heat transfer. The technology was developed by Diemat, a think-tank in Topsfield, MA, and licensed to Ablestik.
Inspectech`s KIS (kerf inspection system) 2000 dicing yield maximizer is a neat little system that automates wafer dicing inspection, perhaps the last holdout of the human eyeball in wafer fabrication. This system automates top- and back-side chip and crack inspection, and brings statistical process control (SPC) to this seemingly straightforward process. The system is already in use at Siemens` Regensburg facility. Werner Kroeninger, a process engineering manager there, said, "[Previous] results with operator inspection are totally unpredictable." Now with SPC after wafer dicing, Kroeminger is able to manage dicing quality and match wafer fabrication`s outgoing inspection with assembly`s incoming inspection. Inspectech and its technology are the brainchild of industry veterans from Kulicke & Soffa and KLA - Avi Ben-Har and Michael Geffen.
Lambda Technologies` MicroCure 5100 attacks flip chip underfill curing time, perhaps the biggest productivity bottleneck in the adoption of this packaging technology. This is a classic example of applying technology from another industry; Lambda has licensed variable frequency microwave technology from Oak Ridge National Laboratory. This technology enables faster cure rates by a factor of ten or more, in 30-40% less floor space, compared to conventional forced convection ovens, and a proportionate savings in energy. There are also dramatic reliability improvements from the technology`s uniform energy distribution and reduction in thermal mismatch on packages in process. The Lamdba system has already been integrated with automated dispense modules from Asymtek. Look for this microwave technology to be applied in other industry applications in the future.
Dupont`s Tacky Dots wafer bumping technology uses an ultraviolet photoimageable adhesive on a Kapton film to form an array of tacky spots that are populated with solder balls. Flooding the film with balls results in each spot holding one ball. Then, this patterned, solder-balled film is aligned with a receiving completed wafer or die and thermal reflow transfers the balls to ICs, essentially bumping the wafer or die. This technology has been used to transfer eutectic solder balls at 350-?m pitch to semiconductor wafers and 150-200-?m high lead balls to leadless chip carriers.
W.L. Gore`s via on-chip pitch packages are touted as a new package category. This technology combines Gore`s Microlam organic dielectric in a laminated form, foil metallization (replacing more expensive physical vapor deposition), laser formed vias, electroless, and electrolytic plating. Vias are placed on the same pitch as flip chip bumps under a given die; this minimizes die size or maximizes I/Os. These new packages target performance-driven flip chip applications. Flip chip devices with bump counts approaching 4000 bumps on pitches as low as 230 ?m have been successfully designed, fabricated, and assembled.
Spherical chips
Ball Semiconductor Inc. sponsored a one-and-a-half day seminar intended to kindle interest in its radical spherical chip-scale process. Ball plans to shoot 1-mm diameter single-crystal silicon spheres through tubes that will accomplish all semiconductor processing except for lithography. Simple devices have been produced, and the ability to pattern aluminum shown (see figure). Lithography is accomplished by orienting each ball on a pedestal in the center of a cup formed of 54 mirrors; light passing through a convoluted pattern on an ordinary chrome mask is reflected off the mirrors to form a de-convoluted pattern on a ball`s surface. Due to depth-of-focus variations between the centers and edges of the mirrors, the company`s test system can only run with a 0.2 NA (limiting resolution to 1.75 ?m using g-line illumination). The company states that a switch to a greater number of smaller mirrors and i-line should allow for 1.0 ?m resolution and the formation of approximately 2500 active gates on each 1.0-mm ball. Company models predict that complete product cycle time will be 5 days, with final parts costing a few cents in full volume production. Though the technology may be feasible, it is still unclear what commercially viable ICs this technology can produce.
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Ball Semiconductor has achieved simple devices on 1-mm silicon balls.